Roteiro O que é ......

08/08/2010
Plataforma de Redes
Reconfigurável (netFPGA)
Cesar Augusto C. Marcondes
Professor Adjunto – UFSCar
PhD UCLA 2008
MSc UFRJ 2003
CCO-129
Hardware Reconfigurável para Redes de
Computadores e Internet do Futuro
Slides baseados na Escola de Primavera de netFPGA 2010 – Cambridge UK
Roteiro
O que é netFPGA?
Como preparar designs integrados de HW e SW
Roteador de Referencia do netFPGA
Configuração de um Lab netFPGA
Pipeline de Referencia
Abordando netFPGA em classe
Desenvolvimento de Projetos do netFPGA
Projetos Já Desenvolvidos em netFPGA
Um Exemplo de Estimadores Passivos em TCP
O que é
.........
Projeto de
Hardware Aberto
(Stanford – Nick
McKeown – EE/CS)
Software de Redes
executando em um
PC comum
Um acelerador em
hardware
construído através
de hardware
reconfigurável
FPGA conduzindo
os enlaces Gigabit
1
08/08/2010
Quem, Como, e Por que?
Quem usa o netFPGA?
estudantes
professores
Pesquisadores
Por que eles usam o netFPGA?
Para medir o desempenho de sistemas Internet
Para prototipar novos sistemas de rede
Como eles usam o netFPGA?
Para executar um roteador típico
Para construir seus módulos a partir das referencias
roteador IPv4
NIC de 4-portas
switch Ethernet
Executando o Roteador (Router Kit)
Desenvolvimento no user-space, comutação a taxa física 4x1GE
OSPF
BGP
Memory
CPU
My Protocol
user
kernel
Routing
Table
PCI
“Mirror”
Fwding
Table
Packet
Buffer
1GE
FPGA
IPv4
Router
1GE
Memory
1GE
1GE
Melhorando os Módulos de Referencia
PW-OSPF
CPU
Memory
Java GUI
Front Panel
(Extensible)
PCI
NetFPGA Driver
1GE
FPGA
1GE
1GE
Memory
Verilog
EDA Tools
(Xilinx,
Mentor, etc.)
1GE
L3
Parse
L2
Parse
1. Design
2. Simulate
1GE
3.
In QSynthesize
4. Download
Mgmt
1GE
IP
Lookup
My
Block
Out Q
Mgmt
1GE
1GE
Verilog modules interconnected by FIFO interfaces
2
08/08/2010
Criando novos sistemas
Verilog
EDA Tools
(Xilinx,
Mentor, etc.)
Memory
CPU
1. Design
PCI
NetFPGA
2. Driver
Simulate
3. Synthesize
4. Download
1GE
FPGA
1GE
My Design
1GE
1GE
1GE
Memory
1GE
(1GE MAC is soft/replaceable)
1GE
1GE
Operação Básica de um Roteador IP
R3
R1
A
R4
D
B
E
R2
C
Destination
Next Hop
D
R3
E
R3
F
R5
R5
F
O que faz um Roteador?
R3
R1
A
1
16
Ver HLen
20 bytes
B
C
R4
4
T.Service
TTL
Total Packet Length
Flags Fragment Offset
Fragment ID
D
32
Protocol
E
Header Checksum
R2
Source Address
Destination
Next Hop
Destination
Address
D
Options
(if any)R3
E
F
Data
R5
F
R3
R5
3
08/08/2010
O que faz um Roteador?
R3
A
R1
R4
D
B
C
E
R2
R5
F
Componentes Básicos de um Roteador IP
Protocolos
Roteamento
Tabela
Roteamento
Software
Gerencia
& CLI
Hardware
Comutação
Tabela de
Propriam.
Comutação
Dita
Control Plane
Datapath
processamento
por-pacote
Processamento por-pacote em um
Roteador IP
1. Aceitar um pacote ingressando no link/porta de
chegada
2. Fazer a busca (Lookup) do endereço de destino
do pacote na tabela de comutação para
identificar o link/porta de saída
3. Manipular o cabeçalho IP: ex., decrementar o
TTL, atualizar o checksum do cabeçalho
4. Bufferizar o pacote na fila de saída
5. Transmitir o pacote no link/porta saída
4
08/08/2010
Arquitetura Genérica do
Datapath de Roteador IP
Header Processing
Data
Hdr
Queue
Packet
Lookup
Update
IP Address Header
IP Address
Data
Hdr
Next Hop
Forwarding
Table
Buffer
Memory
Endereçamento CIDR –
Classless Interdomain Routing
128.9.19/24
128.9.25/24
128.9.16/20 128.9.176/20
128.9/16
232-1
0
128.9.16.14
Rota mais específica = “longest matching prefix”
Técnicas de Longest Prefix
Match em Hardware
Busca Linear
Lento
Lookup Direto
Requer muita memória
Atualizar um prefixo requer
várias mudanças
Prefix Trees
Tempo de Lookup
Deterministico
Facilmente montado em
pipeline com múltiplas
memórias/referencias
TCAM (Ternary CAM)
Simple e amplamente usado
em roteadores mas temos
baixa densidade de RAM e
precisa mais energia
5
08/08/2010
Um Roteador em NetFPGA
Exception
Processing
Software
Management
& CLI
Routing
Protocols
Routing
Table
Hardware
Forwarding
Switching
Table
Processos Linux
User-level
Verilog na placa PCI
NetFPGA
Roteador NetFPGA
Função
4 portas Gigabit Ethernet
Completamente Reprogramável
FPGA hardware
Baixo custo
Open-source FPGA hardware
Com um design de referencia em Verilog
Open-souce Software
Drivers escritos em C e C++
Plataforma NetFPGA v2
Componentes
Interfaces
4 Portas Gigabit Ethernet
Interface PCI Host
Memórias
36Mbits Static RAM (aprox. 4MB)
512Mbits DDR2 Dynamic RAM (aprox. 64MB)
Recursos FPGA
Block RAMs
Configurable Logic Block (CLBs)
Memory Mapped Registers
6
08/08/2010
Sistema Completo NetFPGA
CAD
Tools
Monitor
Software
Web &
Video
Server
Browser
& Video
Client
User Space
Linux Kernel
Packet Forwarding Table
PCI
PCI-e
VI
VI
VI
VI
NIC
NetFPGA Router
Hardware
GE
GE
GE
GE
GE
GE
(nf2c0 .. 3)
(eth1 .. 2)
NetFPGA v2 Hardware
Components
• Xilinx Virtex-2 Pro FPGA for User Logic
• Xilinx Spartan for PCI Host Interface
• Cypress: 2 * 2.25 MB ZBT SRAM
• Micron: 64MB DDR2 DRAM
• Broadcom: PHY for 4 Gigabit Ethernet ports
Sistema Montado NetFPGA
Network Ports
Host PCI-express NIC
Dual Gigabit Ethernet
ports on PCI-express card
NetFPGA
Quad Gigabit Ethernet
ports on NetFPGA PCI card
Motherboard
Standard AMD or Intel-based
x86 computer with PCI
and PCI-express slots
Processor
Dual or Quad-Core CPU
Operating System
Linux CentOS 5.2
7
08/08/2010
Stanford NetFPGA Cluster
Statistics
• Rack de 40
• 1U PCs com
NetFPGAs
•
Provê
4*40=160 Gbps
de banda a taxa
física completa
•
Possível de
montar
topologias
variadas e
colocar grupos
de alunos por
máquina remota
Setup Típico para Ensino
PCI-e
Client
Server
CPU x2
Net-FPGA
PCI
NetFPGA
Control SW
Dual
NIC
(eth1
.. 2)
Internet
Router
Hardware
CAD Tools
GE
eth1 : Local Client & Server
GE
eth2 : Server for Neighbor
GE
nf2c3 : Ring - Left
GE
nf2c2 : Local Host
GE
nf2c1 : Neighbor
GE
nf2c0 : Ring - Right
Setup Típico para Ensino
PCI-e
Video
Server
CPU x2
NIC
Net-FPGA
PCI
Servidor de Vídeo
fazendo o streaming
passando por um
anel de roteadores
NetFPGA
Internet
Router
Hardware
Net-FPGA
Internet
Router
Hardware
GE
GE
GE
GE
GE
GE
GE
GE
GE
GE
…
PCI-e
CPU x2
CAD Tools
Net-FPGA
PCI
Video
Display
NIC
Internet
Router
Hardware
GE
GE
GE
GE
GE
GE
8
08/08/2010
Setup do Roteador Referencia
Video
Server
Cada placa NetFPGA
possui quatro
NetFPGA
Porta 2 conecta Cliente /
ou Servidor
NetFPGA
Ports 0 e 3 conectam
placas NetFPGA
adjacentes
Video
Client
NetFPGA
Configuração de SubRede
Roteamento PW-OSPF
(Pee-Wee OSPF)
.1.1
.4.1
.1.2
.7.1
.4.2
.2.1
.5.1
.9.2
.8.1
.9.1
.11.1
.16.1
.13.2
.12.2
.12.1
.16.2
.15.2
.14.1
.15.1
.17.1
.18.1
Display
.30.1
.29.1
.6.1
.13.1
.10.2
.6.2
.3.2
.30.2
.10.1
.7.2
.3.1
.26.1
.23.1
.27.2
.28.2
.24.2
.27.1
.25.2
.28.1
Video
Server
.18.2
.21.2
.24.1
.25.1
.22.2
.20.1
.21.1
.22.1
Caminho Mais Curto
.19.2
.19.1
Video
Client
Fazendo o Streaming de Video c/ NetFPGA
Servidor de Vídeo
Arquivos depositados em
/var/www/html/video
Acessíveis em:
http://192.168.Net.Host/video
Cliente de Vídeo
Windows Media Player
Linux mplayer
Tráfego de Vídeo
MPEG2 HDTV (35 Mbps)
MPEG2 TV (9 Mbps)
DVI (3 Mbps)
WMF (1.7 Mbps)
9
08/08/2010
Observando as Tabelas de Roteamento
Os roteadores no demo já
estão rodando nas
máquinas
A tabela de roteamento já
convergiu para as decisões
de roteamento com o
mínimo número de hops
Re-roteamento Dinâmico
Quebrando o link entre o
menor caminho do
servidor de vídeo para o
cliente
.1.1
.4.1
.1.2
.5.1
.30.1
.29.1
.10.1
.7.2
.28.1
.8.1
.26.1
.27.2
.28.2
.9.2
.6.1
.11.1
.25.1
.14.
1
.17.1
.18.1
.18.2
.21.2
.24.1
.16.2
.15.2
.15.1
.12.1
.23.1
.25.2
.16.1
.13.2
.12.2
.9.1
.24.2
.27.1
.13.1
.10.2
.6.2
.3.2
.30.2
Roteadores vão re-rotear o
tráfego do outro lado do
anel em torno do link
caido e o vídeo
continuará tocando após
uma leve pausa
.7.1
.4.2
.3.1
.2.1
.22.2
.20.1
.21.1
.22.1
.19.2
.19.1
Tecnologia de Hardware Reprogramável
Field Programmable Gate Arrays
(FPGAs)
10
08/08/2010
Tabelas de Look-Up
A B C D Z
Lógica Combinatorial (adders, etc.) são
armazenados em Look-Up Tables (LUTs)
Também chamados de
0 0 0 0 0
0 0 0 1 0
Geradores de Função (FGs)
0 0 1 0 0
Capacidade é limitada pelo
0 0 1 1 1
número de entradas
0 1 0 0 1
Atraso no LUT é constante
0 1 0 1 1
.
A
B
. .
1 1 0 0 0
Combinatorial Logic
1 1 0 1 0
1 1 1 0 0
Z
C
D
1 1 1 1 1
Diagram From: Xilinx, Inc
Xilinx CLB (Configurable Logic Blocks)
Cada slice tem 4 saídas
Duas saídas são geradas de
registradorese duas saídas
sem registradores (diretas)
Temos BUFTs (tristate buffers)
associados com cada CLB
Lógica de “Carry” (Vai-Um) para
controle, a lógica pode correr
verticalmente
Duas cadeias de carry por
Slice 0
LUT
PRE
D
Q
CE
Carry
CLR
LUT
D PRE
Q
CE
Carry
CLR
CLB
Diagram From: Xilinx, Inc.
Field Programmable Gate
Arrays
Din
Clk
CLB
G1
G2
G3
4 LUT
M
Bloco de I/O
S
Q
YQ
R
M
Y
3 LUT
H1
H
F1
F2
4 LUT
F3
F
M
D
S
Q
XQ
R
M
F4
Módulo de Roteamento
Roteamento global
Interconexão Local
Macro Blocks
Blocos de Memória
Algum co-Microprocessor
D
G
G4
CLB
Elemento Básico do FPGA
X
GRM
Local Routing
CLB
PIP
3rd Generation LUT-based FPGA
...
...
...
...
...
Pad Routing
Macro
Block
(uP,
Mem)
...
...
CLB Matrix
I/O
11
08/08/2010
Diagrama de Blocos NetFPGA
NetFPGA platform
The image cannot be display ed. Your computer may not hav e enough memory to open the image, or
the image may hav e been corrupted. Restart y our computer, and then open the file again. If the red
x still appears, y ou may hav e to delete the image and then insert it again.
Linux OS - NetFPGA Kernel driver
3 Gb
The image cannot be display ed. Your computer
may not hav e enough memory to open the
image, or the image may hav e been corrupted.
Restart y our computer, and then open the file
again. If the red x still appears, y ou may hav e to
delete the image and then insert it again.
SATA
Host
computer
Control, PCI
Interface
Board-Board Interconnect
1GE
PHY
FIFO
packet
buffers
64MB
18Mb
DDR2
SDRAM SRAM
1GE
PHY
Seu hardware especificado
em código Verilog conecta
os componentes
do circuito
do roteador de referencia
18Mb
SRAM
1GE
PHY
1GE 1GE 1GE 1GE
MAC MAC MAC MAC
1GE
PHY
Four Gigabit Ethernet Interfaces
V2-Pro50 FPGA w/ infrastructure
User-defined software networking applications
Linguagens de Descrição de
Hardware
Intrinsicamente concorrente
Por padrão, comandos Verilog
são avaliados concorrentemente
Expressa paralelismo fine grain
Paralelismo nível de portões lógicos
Descrição Precisa do Hardware
Elimina ambiguidade
Sintetizável
Gera um hardware a partir da descrição Verilog
Tipo de Dados /
Multiplexadores
reg [7:0] A; // 8-bit register, MSB to
LSB
// (Preferred bit order for
NetFPGA)
reg [0:15] B; // 16-bit register, LSB to
MSB
B = {A[7:0],A[0:7]}; // Assignment
of bits
Two input multiplexer (using if / else)
reg y;
always @*
if (select)
y = a;
else
y = b;
reg [31:0] Mem [0:1023]; // 1K
Word Memory
integer Count;
bit integer
// simple signed 32-
integer K[1:64]; // an array of 64
integers
time Start, Stop; // Two 64-bit time
variables
From: CSCI 320 Computer Architecture
Handbook on Verilog HDL, by Dr. Daniel C. Hyde :
http://eesun.free.fr/DOC/VERILOG/verilog-manual.html
12
08/08/2010
Elementos de Armazenamento Sincrono
Din
Valores mudam no
tempo governados
pelo clock (125MHz)
D
Q
Dout
Clock
– Clock
Clock 1
Clock Transition
0
t=0
• Entrada no Circuito
t=1
time
t=2
– Eventos de Clock
• Exemplo: Rising edge
Din
A
B
C
t=0
– Flip/Flop
Clock Transition
• Transferem o valor de
Din para Dout (por exemplo,
estágio a outro) no evento
de clock
Dout
S0
A
B
t=0
Verilog: Especificando Delay Flip/Flops
D-type flip flop
reg q;
always @ (posedge clk)
q <= d;
D type flip flop with data enable
reg q;
always @ (posedge clk)
if (enable)
q <= d;
From: http://eesun.free.fr/DOC/VERILOG/synvlg.html
Máquinas de Estado Finitas
Outputs (Z)
Copyright 2001, John W. Lockwood, All Rights Reserved
Inputs (X)
=λ (X,S(t))
[Mealy]
-or-
=λ (S(t))
[Moore]
Combinational Logic
Q D
S(t)
...
S(t+1)=
δ (X,S(t))
Next
State
Q D
State Storage
13
08/08/2010
Pipeline do Roteador de
Referencia
Pipeline do Roteador de Referencia
Cinco Estágios
Input
Arbitração do Input
Decisão de Roteamento e
MAC
RxQ
CPU
RxQ
MAC
RxQ
CPU
RxQ
MAC
RxQ
CPU
RxQ
MAC
RxQ
CPU
RxQ
Input Arbiter
Modificação do Pacote
Enfileiramento na Saída
Output
Output Port Lookup
Interface dos módulos
Output Queues
baseada em Pacote
Design Plugável
MAC
TxQ
CPU
TxQ
MAC
TxQ
CPU
TxQ
MAC
TxQ
CPU
TxQ
MAC
TxQ
CPU
TxQ
14
08/08/2010
Melhorando o Roteador
Objetivos
Observar como estão posicionados os novos módulos
Novos módulos são: limitador de taxa, capturador de
eventos (perdas por exemplo)
Pipeline Roteador Avançado
Dois módulos
adicionados
MAC
RxQ
CPU
RxQ
MAC
RxQ
1. Event Capture para
CPU
RxQ
MAC
RxQ
CPU
RxQ
MAC
RxQ
CPU
RxQ
CPU
TxQ
MAC
TxQ
CPU
TxQ
Input Arbiter
capturar em tempo
real eventos das filas
de saída (writes,
reads, drops)
Output Port Lookup
Event Capture
2. Rate Limiter para
criar um gargalo
(força o tráfego)
Output Queues
Rate
Limiter
MAC
TxQ
CPU
TxQ
CPU
TxQ
MAC
TxQ
MAC
TxQ
Hardware Datapath
Se der tempo …
15
08/08/2010
Full System Components
Software
nf2c0
nf2c1
nf2c2
nf2c3
ioctl
PCI Bus
CPU CPU
CPU
CPU
CPU
CPU TxQ
RxQ
CPU
CPU
RxQ
TxQ
RxQ
TxQ
RxQ
TxQ
NetFPGA
nf2_reg_grp
user data path
MAC MAC
MAC
MAC
MAC
MAC
TxQ MAC
RxQ
MAC
TxQ
RxQ
TxQ
RxQ
TxQ
RxQ
Ethernet
Life of a Packet through the
Hardware
192.168.1.x
port0
192.168.2.y
port2
Router Stages Again
MAC
RxQ
CPU
RxQ
MAC
RxQ
CPU
RxQ
MAC
RxQ
CPU
RxQ
MAC
RxQ
CPU
RxQ
Input Arbiter
Output Port Lookup
Output Queues
MAC
TxQ
CPU
TxQ
MAC
TxQ
CPU
TxQ
MAC
TxQ
CPU
TxQ
MAC
TxQ
CPU
TxQ
16
08/08/2010
Inter-Module Communication
Using “Module Headers”:
Ctrl Word
(8 bits)
Data Word
(64 bits)
x
Module Hdr
…
…
y
Last Module Hdr
0
Eth Hdr
0
IP Hdr
0
…
0x10
Last word of packet
Contain information
such as packet length,
input port, output port,
…
Inter-Module Communication
data
ctrl
wr
rdy
MAC Rx Queue
17
08/08/2010
Rx Queue
0xff
0
0
0
Pkt length,
input port = 0
Eth Hdr:
Dst MAC = port 0,
Ethertype = IP
IP Hdr:
IP Dst: 192.168.2.3, TTL:
64, Csum:0x3ab4
Data
Input Arbiter
Pkt
Pkt
Pkt
Output Port Lookup
18
08/08/2010
Output Port Lookup 5- Add output
1- Check input
port matches
Dst MAC
port header
2- Check TTL,
checksum
0xff
3- Lookup next
hop IP & output
port (LPM)
0
0
4- Lookup next
hop MAC
address (ARP)
0
Pkt length,
input port = 0
output port = 4
EthHdr:
MAC
=0
EthHdr:
Dst Dst
MAC
= nextHop
MAC
= x, 4,
SrcSrc
MAC
= port
Ethertype = IP
IP Hdr:
IP Dst: 192.168.2.3, TTL:
64,
63, Csum:0x3ab4
Csum:0x3ac2
6- Modify MAC
Dst and Src
addresses
7-Decrement
TTL and update
checksum
Data
Output Queues
OQ0
OQ4
OQ7
MAC Tx Queue
19
08/08/2010
MAC Tx Queue
0xff
0
0
Pkt length,
input port = 0
output port = 4
EthHdr: Dst MAC = nextHop
Src MAC = port 4,
Ethertype = IP
IP Hdr:
IP Dst: 192.168.2.3, TTL:
64,
63, Csum:0x3ab4
Csum:0x3ac2
0
Data
Exception Packet Path
Software
nf2c0
nf2c1
nf2c2
nf2c3
ioctl
PCI Bus
CPU CPU
RxQ TxQ
CPU CPU
RxQ TxQ
NetFPGA
CPU CPU
RxQ TxQ
nf2_reg_grp
CPU CPU
RxQ TxQ
user data path
MAC MAC
TxQ RxQ
MAC MAC
TxQ RxQ
MAC MAC
TxQ RxQ
MAC MAC
TxQ RxQ
Ethernet
Output Port Lookup
1- Check input
port matches
Dst MAC
2- Check TTL,
checksum –
EXCEPTION!
0xff
0
3- Add output
port module
0
0
Pkt length,
input port = 0
output port = 1
EthHdr: Dst MAC = 0,
Src MAC = x,
Ethertype = IP
IP Hdr:
IP Dst: 192.168.2.3, TTL:
1, Csum:0x3ab4
Data
20
08/08/2010
Output Queues
OQ0
OQ1
OQ2
OQ7
CPU Tx Queue
CPU Tx Queue
0xff
0
0
0
Pkt length,
input port = 0
output port = 1
EthHdr: Dst MAC = 0,
Src MAC = x,
Ethertype = IP
IP Hdr:
IP Dst: 192.168.2.3, TTL:
1, Csum:0x3ab4
Data
21
08/08/2010
ICMP Packet Path
Software
nf2c0
nf2c1
nf2c2
nf2c3
ioctl
PCI Bus
CPU CPU
RxQ TxQ
CPU CPU
RxQ TxQ
CPU CPU
RxQ TxQ
NetFPGA
nf2_reg_grp
CPU CPU
RxQ TxQ
user data path
MAC MAC
TxQ RxQ
MAC MAC
TxQ RxQ
MAC MAC
TxQ RxQ
MAC MAC
TxQ RxQ
Ethernet
NetFPGA-Host Interaction
Linux driver interfaces with hardware
Packet interface via standard Linux network stack
Register reads/writes via ioctl system call
with wrapper functions:
readReg(nf2device *dev, int address, unsigned *rd_data);
writeReg(nf2device *dev, int address, unsigned *wr_data);
eg:
readReg(&nf2, OQ_NUM_PKTS_STORED_0, &val);
NetFPGA-Host Interaction
NetFPGA to host packet transfer
1. Packet arrives –
forwarding table
sends to CPU queue
PCI Bus
2. Interrupt
notifies
driver of
packet
arrival
3. Driver sets up
and initiates DMA
transfer
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08/08/2010
NetFPGA-Host Interaction
NetFPGA to host packet transfer (cont.)
5. Interrupt
signals
completion
of DMA
PCI Bus
4. NetFPGA
transfers
packet via
DMA
6. Driver passes packet to
network stack
NetFPGA-Host Interaction
Host to NetFPGA packet transfers
PCI Bus
2. Driver sets up
and initiates DMA
transfer
3. Interrupt
signals
completion
of DMA
1. Software sends packet
via network sockets
Packet delivered to driver
NetFPGA-Host Interaction
Register access
PCI Bus
2. Driver
performs
PCI memory
read/write
1. Software makes ioctl
call on network socket
ioctl passed to driver
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08/08/2010
NetFPGA-Host Interaction
Packet transfers shown using DMA interface
Alternative: use programmed IO to transfer packets via
register reads/writes
slower but eliminates the need to deal with network
sockets
Ensinado com o
netFPGA
Construir um roteador em 10 semanas
Usando NetFPGA em Sala de
Aula (Graduação)
•
Stanford University
• EE109 “Build an Ethernet Switch”
•
•
Cambridge University
• Build an Internet Router (since ‘09)
Undergraduate course for all EE
students
Quarter-long course targeted at
graduates
http://www.stanford.edu/class/ee109/
http://www.cl.cam.ac.uk/teaching/0910/
P33/
CS344 “Building an Internet Router”
(since ‘05)
Quarter-long course targeted at
graduates
http://cs344.stanford.edu
•
University of Wisconsin
• CS838 “Rethinking the Internet
Architecture”
•
Rice University
• Network Systems Architecture (since
http://pages.cs.wisc.edu/~akella/CS838
/F09/
‘08)
http://comp519.cs.rice.edu/
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08/08/2010
NetFPGA em Sala de Aula
Stanford CS344: “Build an Internet Router”
Todo o material desse curso está online
Estudantes trabalham em equipes de 3 sendo
1-2 software
1-2 hardware
Objetivo é Projetar e Implementar um Roteador em 8
Semanas
Escrever o software de interface e PW-OSPF
Mostrar que o design interopera com outros grupos
Adicionar novas caracteristicas nas 2 semanas restantes
Firewall, NAT, DRR, Packet capture, Data generator, …
CS344 Milestones
1
2
Build basic router
3
4
Command Line Routing Protocol
Interface
(PWOSPF)
5
Integrate with H/W
6
Interoperability
Final Project
Management
& CLI
Exception
Processing
Routing
Protocols
Management
& CLI
Routing
Table
Exception
Processing
Emulated
h/w in VNS
Management
& CLI
Routing
Protocols
Routing
Table
Routing
Protocols
• Innovate and add!
• Presentations
• Judges
Exception
Processing
Routi ng
Table
Emulated
h/w in VNS
Emulated
h/w in VNS
Management
& CLI
Exception
Processing
software
hardware
Routing
Protocols
Routing
Table
Forwarding
Switching
Table
Learning Environment
Modular design
Testing
4-port non-learning
switch
Forwarding
Switching
Table
4-port learning
IPv4 router
switch
forwarding path
Integrate with S/W
Interoperability
Typical NetFPGA Course Plan
Week
Software
Hardware
Verify Software Tools
2
Build Software Router
Build Non-Learning
Switch
Run Software Router
3
Cmd. Line Interface
Build Learning Switch
Run Basic Switch
4
Router Protocols
Output Queues
Run Learning Switch
5
Implement Protocol
Forwarding Path
Interface SW & HW
6
Control Hardware
Hardware Registers
7
Verify CAD Tools
Deliver
1
Interoperate Software & Hardware
Write Design
Document
HW/SW Test
Router Submission
8
Plan New Advanced Feature
Project Design Plan
9
Show new Advanced Feature
Demonstration
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08/08/2010
Apresentações
Stanford CS344
http://cs344.stanford.edu
Cambridge P33
http://www.cl.cam.ac.uk/teaching/0910/P33/
Pesquisa com o
netFPGA
Desenvolvendo a sua tese com netFPGA
Projetos de
Pesquisa
IPv4 Reference Router
Stanford University
Quad-Port Gigabit NIC
Stanford University
Ethernet Switch
Stanford University
Buffer Monitoring System
Stanford University
HW-Accelerated Linux Router
Stanford University
Packet Generator
Stanford University
OpenFlow Switch
Stanford University
NetFlow Probe
Brno University
AirFPGA
Stanford University
Multipath Router
Stanford University
Precise Traffic Generator
University of Torontoz
RED
Stanford University
DFA
UMass
RCP Router
Stanford University
Deficit Round Robin (DRR)
Stanford University
OpenFlow-MPLS Switch
Ericsson
PTP-enabled Router
Stanford University
Vlan Tag Handler
Stanford University
Port Aggregator
Stanford University
IP Lookup w/Blooming Tree
University of Pisa
Tunneling NIC
Stanford University
End-to-End Ethernet Authoriz.
Euskal Herriko Unibertsitateko
Ultra-high Speed Cong.-control
University of North Carolina
26
08/08/2010
Exemplo: AirFPGA
TCP-based Passive
Bottleneck Estimation
Cesar & Peng
Outline of intention
To build a router that passively monitors ACK flows
Based on slow start pattern
Estimate bottleneck capacity per flow
Cap flows based on the calculation by modifying their
TCP receive window.
27
08/08/2010
BitTorrent
Scenario
Online
gaming
Buffer filling
Cwnd = min (cwnd, rcvwnd)
One could limit max rate by
implicitly change the rcvwnd
C= L
Tb
ACK flow (packets back to back
in every RTT during slow start)
CapProbe algorithm
Sigcomm 2004
Exploring Embedded Path Capacity Estimation in TCP receiver
E2EMON 2007
28
08/08/2010
Design
Mod_Hdr, Eth_Hdr:
Estimator
skip the blocks we don’t care
Prot_field, Dst_IP field:
Deep inspection in the pkts
to filter ACK flow from dst &
port
Filtering TCP pkts from
specific IP dst, ACK&SYN
flag and TCP port
Counters:
Clk_counter for clk cycles
Pkt_slice as field locator
Pkt_counter done at the
Wait4end state to allow for
selecting specific ACK pkts to
timestamp (1,2 .. 3,4, .. 7,8)
Simulation
Couldn’t get it done …
IP DST filter still has some bugs
Capprobe Calculation in hardware difficult
Division by dispersion
Change TCP receive window
Cannot be done without re-calculate TCP checksum
Cesar is planning to finish this work
Lessons learnt
Bad:
need hardware design experience
Lots of languages required (verilog, perl)
Good:
fairly easy to generate simulation test
Reuse code (drop-nth-packet, crypto_nic)
29
08/08/2010
Futuro do netFPGA
Redes de Alta Velocidade
NetFPGA 10G: (Coming in 3rd Qtr 2010)
QDRII+ SRAM
3x 36bit interfaces, 300MHz+
(each i/f: 1x K7R643684MFC30)
SFP+
Cage
SFP+
Cage
SFI
10Gbps
PHY
AEL2005
XAUI
4 GTXs
SFI
10Gbps
PHY
AEL2005
XAUI
4 GTXs
SFP+
Cage
SFI
10Gbps
SFP+
Cage
SFI
10Gbps
PCIe x8, Gen1
endpoint edge
connector
Xilinx Virtex5
XCV5TX240T-2
PHY
AEL2005
XAUI
4 GTXs
PHY
AEL2005
XAUI
4 GTXs
NetFPGA 10G
PCIe
8 GTXs
FG1759
10 GTXs
10 GTXs
2 x Samtec
x10 Connector
RLDRAM II
2x 32bit interfaces, 300MHz+
Obrigado …
Cesar Marcondes
[email protected]
http://www.dc.ufscar.br/~marcondes/
30