relatório de progresso - INESC-ID

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PROJECTOS DE INVESTIGAÇÃO CIENTÍFICA E DESENVOLVIMENTO TECNOLÓGICO
RELATÓRIO DE PROGRESSO
Relatório de Execução Material
Relatório de Execução Financeira
REFERÊNCIA DO PROJECTO Nº __ POSC/EEA-CPS/59401/2004
RELATÓRIO REFERENTE AO ___2__º ANO DE EXECUÇÃO
União Europeia – Fundos Estruturais
Governo da República Portuguesa
Data de Entrada_____________________
Nº de Registo ______________________
Data de Verificação__________________
Assinatura ________________________
Espaço reservado à Fundação para a Ciência e a Tecnologia
Referência do projecto: POSC/_EEA-CPS/_59401/_2004__
Título do projecto:
Sistema de Comunicação OFDM Adaptativo na Rede de
Distribuição de Energia Eléctrica
Data de Início do Projecto: __1__/___Abril______/__2005__
Duração: _24___ Meses
Identificação da instituição proponente
Nome ou designação social Instituto de Engenharia de Sistemas e Computadores, Investigação e
Desenvolvimento em Lisboa (INESC-ID)
Morada R. Alves Redol, 9
LocalidadeLisboa
Telefone 213100300
Código postal 1000-029
Fax 213145843
Email [email protected]
Unidade responsável pela execução do projecto
Nome Sistemas de Processamento de Sinal
Morada R. Alves Redol, 9
LocalidadeLisboa
Telefone 213100300
Código postal 1000-029
Fax 213145843
Identificação do investigador responsável
Nome José António Beltran Gerald
Telefone 213100368
Fax 213145843
Instituições que participam no projecto
(preencher só em caso de haver alterações)
DESIGNAÇÃO
Instituição 1
Instituição 2
Instituição 3
Instituição 4
Equipa de investigação
(preencher só em caso de haver alterações)
NOME
CARGO/FUNÇÃO
TAREFAS
%TEMPO
Esforço global do projecto, expresso na unidade pessoa*mês
(referente ao ____2º____ ano de execução)
Unidade: em número
Instituição Proponente
17,1
Instituição 1
5,2
Instituição 2
Instituição 3
Instituição 4
Resumo dos trabalhos desenvolvidos
No período aqui relatado, decorreram as Tarefa 1 - "Power Line Model
Validation" (de 1de Janeiro a 31 de Março de 2006), Tarefa 2 - "Comparative study
of Coding Schemes and Digital Modulation Techniques" (de 1 de Janeiro a 31 de
Dezembro de 2006) e Tarefa 3 - "Adaptive Communication Techniques" (de 1 de
Janeiro a 31 de Dezembro de 2006).
Os trabalhos visaram os objectivos das respectivas tarefas, especialmente a de
validação do modelo a adoptar para a linha de distribuição de energia, objectivo que
se tem revelado bastante mais difícil de concretizar devido ao complexo hardware
necessário. Também, foi continuada a realização de um sistema de simulação em
computador para estudo das técnicas OFDM, necessário à execução das restantes 2
tarefas.
Tarefa 1:
No referente à primeira tarefa, foi realizado um novo modem PLC em
hardware para acoplamento à linha de distribuição de energia eléctrica. Este novo
modem-protótipo tem a vantagem, sobre o circuito inicialmente utilizado, de ser
modular, permitindo uma relativa independência entre os módulos Interface de
Linha (AFE- Analog Front End), Processamento de Sinal (DPB - Data Processing
Board) e Fontes de Alimentação (PSB - Power Supply Board) (o que se requer num
circuito para desenvolvimento e teste de soluções), para além do modem poder ser
ligado a um utilizador externo via USB. Foram realizadas experiências com a linha
de 220 V. As experiências realizadas não foram contudo suficientes para
caracterização completa da linha. Desta forma, esta tarefa não está completamente
encerrada. Dos resultados obtidos nesta tarefa foi submetida uma comunicação em
conferência internacional (ISCAS'07).
Tarefa 2:
No referente à Tarefa 2 (esta tarefa deveria ter terminado a 30 de Setembro de
2006 mas ainda continua, em parte devido à interrupção que ocorreu na bolsa de
iniciação à investigação, por desistência do primeiro bolseiro), foi continuado a ser
desenvolvido um sistema base de simulação em computador (utilizando o programa
Matlab com Simulink) de comunicação na linha de distribuição de energia eléctrica
usando OFDM, tendo sido acrescentado uma parte de recuperação de sincronismo
no receptor. Também, foi recentemente acrescentada uma parte do simulador
correspondente à codificação do sinal OFDM, nomeadamente no que se refere à
utilização de Turbo Codes ou Low-Density Parity-Check Codes. Foi assim
continuado o desenvolvimento da aplicação computacional.
Tarefa 3:
No referente à Tarefa 3, foi continuado o desenvolvimento de técnicas
adaptativas para melhorar a comunicação com OFDM. Foram desenvolvidos novos
algoritmos adaptativos (o Kalman LMS e suas simplificações) e um novo
equalizador adaptativo com cancelamento de ruído cruzado entre as sub-bandas de
OFDM. Dos resultados obtidos nesta tarefa foram submetidas 2 comunicações em
conferências internacionais (ICASSP'07 e ISCAS'07).
Indicadores de realização física
(Referente ao _2º____ ano de execução)
Unidade: em número
A- Publicações
Livros
Artigos em revistas internacionais
Artigos em revistas nacionais
B- Comunicações
Em congressos científicos internacionais
2
Em congressos científicos nacionais
C- Relatórios
D- Organização de seminários e conferências
1
E- Formação Avançada
Teses de Doutoramento
Teses de Mestrado
Outra
F- Modelos
G- Aplicações computacionais
1
H- Instalações Piloto
I- Protótipos laboratoriais
1
J- Patentes
L- Outros (discriminar) Relatório de Bolsa de Investigação
1
Publicações
(listar as publicações com origem no projecto)
PUBLICAÇÕES
[1] PAULO LOPES, GONÇALO TAVARES, JOSÉ GERALD, “A New Type of
Normalized LMS Algorithm Based on the Kalman Filter”, submitted to ICASSP’07.
[2] PAULO LOPES, JOSÉ GERALD, “New Normalized LMS Algorithms Based
on the Kalman Filter”, submitted to ISCAS’07.
[3] PAULO LOPES, “Survey of Adaptive OFDM and Application to the Power
Line Channel”, INESC-ID Seminar, October 2006.
[4] ANTÓNIO NUNES, “Power Line Communication System using Adaptive
OFDM",Relatório da parte realizada da bolsa de iniciação à investigação científica
no âmbito do projecto POS_C/EEA-CPS/59401/2004 – Power Line Communication
System using Adaptive OFDM, Dezembro de 2006.
RELATÓRIO DE EXECUÇÃO MATERIAL
(incluir o relatório de execução material elaborado de acordo com as normas)
Authors:
José A. B. Gerald
Gonçalo N. G. Tavares
Luis Miguel G. Tavares
Paulo A. C. Lopes
José Vaz
Relatório de Execução Material
( in english)
Objectives (as stated in the proposal):
The main objective of this research project is the study and simulation of a
digital communication system over power lines using OFDM-like multicarrier
technology, and operating with data-rates above 1 Mbps.
The tasks to be performed in this project will lead to a deep understanding of
the power line transmission medium. The characterization of the transmission
medium will also provide a mathematical model for the communication channel.
The identification of digital modulation schemes for OFDM subcarrier
modulation, which best suits the specific problems in PLC is also one of the key
objective of this project.
Another objective is the development of new OFDM coding techniques that will
effectively mitigate the adverse effect of the channel. These techniques will allow
reliable transmission even in the presence of deep spectral nulls in the channel
transfer function and will provide a blind channel identification algorithm.
The development of a custom, user-friendly and versatile software simulation
tool, specific tailored to the PLC environment, is also an important goal of this
project.
Task 1 - Power Line Model Validation (01-04-2005 to 31-032006)
To find the theoretical models that best fit the experimental results already
available by the project team and some yet to be obtained.
Results at month 12:
The work in this task began by implementing a hardware system to interface
with the power lines. The system was implemented (almost all) and experimental
results were obtained. Results obtained till month 9 were already presented in 1st year
report. Next a new PLC modem development and new results obtained with this
improved version are presented.
1.1 PLC modem – Version II
In this work we improved the PLC Modem for domestic communication,
including software for easy handling, using the adequate modulation for data power
line communication.
The idea of a PLC communication is to add a broadband signal to the 50 Hz
signal of the power line. This modulated signal does not affect in any way the normal
work of the domestic electric/electronic devices or industrial machines since the
signal power is insignificant.
The normal indoor power line layout, with its several plugs and domestic
devices that may be connected to them, cause a lot of interference in this
communication channel. Therefore, the use of a modulation which manages the noise
elimination in an effective manner is required. For this purpose we tried to implement
an adequate modulation such as OFDM. Unfortunately, there was no time to obtain
full experimental results with OFDM and the power line. The work towards the final
PLC modem prototype still goes on.
The previous PLC modem circuitry already performs the 220 V network
coupling and A/D and D/A transmitted data conversion. The expected channel
bandwidth goes from 1 MHz to 20 MHz. The bottom frequency is due to the
generated noise by other appliances, which is not filtered by any kind of device in the
network, and the top frequency is due to either the electric network frequency
response or the transformer bandwidth.
The present work consists in implementing the modem control system and
OFDM modulator/demodulator and a Universal Serial Bus (USB) interface with the
user. For simplicity it will be used USB 1.1 specification. The transmission rate
should be no less than 1 Mbps. The emitted OFDM signal center frequency of 4 MHz
was chosen after some experiences with the AFE. Some attention was paid to the
emitted signal power: It does not go over 30 µV/m in a 30 m distance above 3.5 MHz,
which correspond to a -86dBW (-56dBm) level (according to the US FCC Part 15
standards, also used in Europe) [1].
For data processing implementation it was chosen a Field-Programmable Gate
Array (FPGA) instead of a Reduced Instruction Set (RISC) processor, because the
former is faster. The chosen FPGA was considered for its capability of executing
FFT/IFFT very fast. Fig. 1.1 shows the PLC modem architecture.
Power
Modem
USB
Memory
FPGA
AFE
Extra: communication plugs and buttons
Fig. 1.1 – PLC Modem architecture simplified diagram.
Along with the required modem circuitry, other facilities were implemented
with the goal of creating a "demoboard", suitable for testing other modem
alternatives. So, this FPGA has in fact more outputs then those strictly needed, and
the board has a Series protocol DB9 connector and a parallel protocol DB25
connector. The FPGA is connected to a 4 Mb Xilinx memory through a JTAG
connection in order to keep its firmware. This data processing unit is dedicated to
modulate/demodulate the data and connect to the user by means of an 8-bit USB
circuit (for its simplicity). With the implemented circuit the transmission rate is up to
8 Mbps.
Fig. 1.2 shows the signal path (AFE excluded) in the considered OFDM PLC
transmission. Except for the Line path, all the signal processing is performed in the
FPGA board.
Input
QPSK
Modulation
Series/Parallel
IFFT
Parallel/Series
Carrier
Multiplication
Echos
Carrier
Multiplication
Noise
Line = Unknown channel
Output
Series/Parallel
FFT
Demodulation
Parallel/Series
Fig. 1.2 – Signal path in the OFDM PLC transmission.
Next the modem main units are presented, i.e., the Analog Front End (AFE),
the Data Processing Board (DPB), and the Power Supply Board (PSB).
A) Analog Front End (AFE)
Starting with the AFE Board, which connects to the Data Processing Board
through a 26 pin socket and flat cable. The AFE block diagram and AFE board are
shown in Fig. 1.3 and Fig. 1.4, respectively. The AFE is composed by:
• Analog-to-Digital Converter (ADC)
• Digital-to-Analog Converter (DAC)
• Lowpass Filters
• Automatic Gain Control (AGC)
• Bandpass Fiters
• Line Drivers
• Coupling Circuitry
I/O Gate (26 pins)
ADC
10bit
AGC
DAC
LPF
BPF
Driver
Transformer
Fig. 1.3 – AFE block diagram.
Output stage
Transistors
50Hz Filtering
Capacitors
Transformer
1:1
DAC
Filters ICs
Connector (26 pins)
AGC
Fig. 1.4 – AFE board.
As shown in Fig. 1.3, the 26-pin connector is used for a 10-bit data bidirectional bus, a clock signal, an emission signaling bit (connected to a LED), a
reception signaling bit (connected to a LED) and 3 gain control signal bits for the
AGC. All communication between the AFE and the Data Processing Board is
synchronized by the FPGA, with the help of a crystal oscillator implemented in the
Data Processing Board.
B) Data Processing Board (DPB)
In the Data Processing Board one can find the following components:
• FPGA Xilinx Spartan 3 XC3S1000
• Xilinx XC18v04 memory
• 120MHz oscillator
• USB circuit FTDI FT245BM
• Microchip memory 93LC46
• 6 MHz crystal for the USB FTDI
• Transceiver RS232 MAXIM M3386E and DB9 connector for series
interface
• Transceiver Philips 74ALVC16245 and DB25 connector for parallel
interface
• 8 LEDs (red)
• 8 Dipswitches
• 5 pressure buttons
Xilinx advises the XC18v04 memory for programming the 1000 kgates FPGA.
Pressure buttons serve for FPGA testing, by choosing input debug bits, as well as the
red LEDs connected to the FPGA outputs. The parallel connection may serve for slow
communication (in both directions) using the transceiver direction control bit.
Fig. 1.5 shows the Data Processing Board.
RS232
Parallel Connector
Oscillator
USB
Transceiver
FPGA
JTAG
Memory
Pressure
Buttons
Dipswitches
Leds
AFE
Connector
Fig. 1.5 – Data Processing Board of the PLC modem.
The FPGA is the DPB main processing unit, and it interacts with all the circuits
around. Fig. 1.6 illustrates the FPGA connections. One can see in Fig. 1.6 that there is
no direct communication among the surrounding circuits. All communication is
established through the FPGA. The communication between the digital gates and the
AFE is controlled by the FPGA firmware. The 120 MHz signal from the crystal
oscillator is used as clock, for instance for the FPGA and for the AFE converters. The
only exception is the USB circuit, which has its own clock.
Note that the flash memory connected to the FPGA, where its firmware is
stored, can also be used for storing program data, depending on the implemented
program.
JTAG
EEPROM
USB
AFE
Connector
(26 Pins)
FPGA
Series
Connector
Clock
Parallel Connector
Figura 1.6 – FPGA connections block diagram.
Table 1.1 illustrates the connection among all the ICs' pins.
The USB circuit was implemented with the FTDI FT245BM circuit. The USB
unit schematic and functional blocks can be seen in Fig. 1.7 and Fig. 1.8, respectively.
It has an 8-bit input/output bus and several control bits. Fig. 1.9 and Fig. 1.10 show
the connections between the other circuits of the USB unit.
The series connection is implemented by the Maxim MAX3386E transceiver
and the 9-pin DB9 socket, which connect to the input and output transmission signal
pins. It were used the T3 and R1 signal lines (which correspond to pins 9-15 and 1114, respectively).
Transceiver
USB
D0
D1
D2
D3
D4
D5
D6
D7
RD#
WR
TXE#
RXF#
SI/WU
PWREN#
FPGA
A4
A3
B1
C1
D1
E1
G1
H1
J1
K1
M1
N1
P1
R1
Pressure
Buttons
S1
S2
S3
S4
S5
Dipswitches
DS0
DS1
DS2
DS3
DS4
DS5
DS6
DS7
FPGA
LEDs
FPGA
T5
R4
T4
R3
T3
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
RS232
TX
RX
J16
K15
K16
L15
M16
N16
P15
P16
R6
T7
R7
T8
T9
R9
T10
R10
Parallel
Connector
D0
D1
D2
D3
D4
D5
D6
D7
FPGA
AFE
FPGA
H16
G16
G15
E16
E15
D16
D15
C16
OSCILATOR
A8
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
CLK
TX_EN
RX_EN
GAIN_A0
GAIN_A1
GAIN_A2
T12
R13
R11
N15
M15
B14
B13
A14
A13
A10
B16
A12
A9
R16
R12
T14
A5
A7
Table 1.1 – FPGA pin-out.
Figura 1.8 – USB chip functional blocks
Fig. 1.7– Schematic
Fig. 1.9– Connection to
the USB chip memory
Fig. 1.10–USB and Power socket connections
Fig. 1.11 shows the usual connection of the MAX3386E circuit, with the
required capacities for the RS-232 transmission line adaptation.
Fig. 1.11– RS232 transceiver connection.
C) Power Supply Board (PSB)
In order to make the PLC modem the most modular possible, the power supply
circuitry was implemented in a separate board. In this board all the required voltages
will be generated from the 220 V AC signal. The AFE board needs +5V, -5V, and
+3,3V; the DPB needs +1,2V, +2,5V and +3,3V. First the 220V AC signal must be
converted in a DC low voltage one. This is accomplished with the help of a
transformer plus a rectifier bridge and some capacitors, as shown in Fig. 1.12 (TP6
and TP7 inputs are connected to the mains).
1
TP7
MAIN2
5
TP6
MAIN1
6
7
10
9
T1
TRANS5
DGND
-9V
AC2
C8
10uF +
DGND
D1
BRIDGE
AC2 AC1
V-
C9
2200uF
DGND
V+
+9V
AC1
+
+ C10
2200uF
DGND
C11
10uF
DGND
Fig. 1.12–AC/DC Converter circuit.
In order to generate the +5V and the -5V it were used the LM317 and LM337
voltage regulators, respectively, as shown in Fig. 1.13.
U6
+9V
IN
VDD_+5V
2
OUT
ADJ
3
1
+ C19
100uF
C21
100nF
R11
240R
LM317T
R9
240R
+ C23
10uF
R10
240R
+ C24
10uF
C25
100nF
DGND
U5
2
1
C26
100nF
C22
100nF
Vin
ADJ
+ C20
100uF
R12
240R
Vout
3
LM337T
-9V
VDD_-5V
Fig. 1.13 – Power source (+5V, -5V) circuit.
The positive voltage circuit (+5 V) functioning is as follows: C19 and C21
capacitors are used to eliminate some residual signal fluctuations. The LM317 circuit
has a 1.25 V reference signal, which allows to obtain at its output a DC signal with
amplitude given by

R 
VDD + 5V = 1.251 + 9 
R11 

(1.1)
The negative voltage circuit has a similar functioning. Although the negative
voltage signal follows right after to the AFE board, the positive voltage signal is still
used as reference for the lower voltage regulators of this board.
The 3.3V is obtained with the circuit shown in Fig. 1.14, which uses the
LT1761ES5-BYP IC. The 2.5V and 1.2V are obtained with similar circuitry.
TP1
PROBE TEK DPO
T2
VDD_3V3
7
BD139
U2
2
1
10uH 60MHz
U1
LT1761ES5-BYP
IN
OUT
C1
10uF
GND
BYP
ADJ
6
5
3
3
R3
C2
10nF
R1
2K7
4
R21
330R
DGND
2K
C3
3.3uF
AD797AR
+ C4
10uF
DGND
R4
+ C7
100R
10uF
4
L1
2
+5V
C6
100nF
C5
100nF
DGND
R2
47K
DGND
Fig. 1.14 Power source (+3.3V) circuit.
Once again the output voltage for the 3.3V circuit is given by
R1 

VDD 3V 3 = 0.661 +

 R2 
(1.2)
It was necessary to use a feedback architecture for these power supplies
because the maximum output current for the regulators is about 100 mA, which has
revealed not to be enough for the AFE and the DPB all together.
To note that the R21 resistor is extremely important, because the regulator
must have always some output current to ground. Also, R3, C3, C4 and C5 serve for
filtering purpose only, attenuating the high-frequency components at the amplifier
input. This amplifier has a very low output noise (0.9nV/√Hz) and low distortion (120 dB of THD at 20 kHz), and its purpose is only to function as a voltage follower,
being the BD139 transistor the one responsible for all the output current required.
The 1.2V circuit was implemented with the TPS72201 circuit from Texas
Instruments.
Fig. 1.15 shows the Power Supply Board with its main blocks identification.
Transformer
Other Voltage
Regulators
Rectifier bridge
+5V and -5V
Regulators
Output
Transistors
Fig. 1.15– Power Supply Board.
Experimental Results
The required VHDL code for implementing the OFDM data processing and
AFE control was introduced in the FPGA. Some experimental results were obtained
in order to confirm the modem performance.
The transmitted OFDM signal in time can be observed in Fig. 1.16. In this
figure one can differentiate the OFDM amplitude signal variation, which is typical in
this type of modulation. A detail of this figure can be observed in Fig. 1.17, where one
can better see the signal transitions. The OFDM signal is centered at 3.7675 MHz, as
expected, as can be confirmed in Fig. 1. 18. This figure shows the OFDM transmitted
signal spectrum.
Fig. 1.16– OFDM transmitted signal in time.
Fig. 1.17 – Detail of the OFDM transmitted signal in time.
Fig. 1.18 – OFDM transmitted signal spectrum
In these experiences the carrier had peak-to-peak maximum amplitude of 16
mV and the modulating signal had peak-to-peak maximum amplitude of 8 mV. One
can also observe that the SNR at the Channel is high (although it was not measured).
Other experiences were made with the test pressure buttons and the red LEDs,
which confirmed the DPB good functioning, especially in what concerned the USB
circuitry.
Next, some relevant results from the ModelSim compilation report obtained in
the FPGA programming task are presented in Table 1.2. In those results one can see
the Spartan 3S1000 ft256 FPGA is far from being full, remaining much space for
more data processing implementation. For instance, with 64-points IFFT and no USB
communication, the occupied portion rounds the 15% of its full capacity. Although
not yet accomplished, we believe that there is enough capacity in the FPGA for
implementing the full emitter/receiver plus the USB communication.
Timing Summary:
Speed Grade: -5
Minimum period: 9.593ns (Maximum Frequency: 104.239MHz)
Device utilization summary:
Selected Device : 3s1000ft256-5
Number of Slices:
555
out of
7680
7%
Number of Slice Flip Flops:
809
out of
15360
5%
Number of 4 input LUTs:
942
out of
15360
6%
27
out of
173
15%
Number of BRAMs:
3
out of
24
12%
Number of MULT18X18s:
5
out of
24
20%
Number of GCLKs:
2
out of
8
25%
Number used as logic: 864
Number used as Shift registers: 78
Number of bonded IOBs:
IOB Flip Flops: 1
Table 1.2 - ModelSim report detail for the FPGA programming.
Fig. 1.19 shows the full PLC modem, already assembled in 3 boards.
Data Processing Board
Connection plug
Power Supply Board
AFE Board
Plug for 230V 50Hz
Fig. 1.19 – Full Modem
1.2. Line Model
A general description and characterization of the power line communications
(PLC) channel is not feasible due to the variety of lines and cable types presented in a
home network.
Despite this general agreed difficulty, several studies have attempted to achieve
a simulation model characterization of the power line. The main parameters affecting
the power line characterization are the channel impedance, signal attenuation and
interferences and noise.
Channel Impedance varies from place to place due to lines and cable
characteristics and also the network topology, as also with the loads connected at each
time to the network. This issue causes multipath signal propagation, thus degrading
communication performance.
The Signal Attenuation is caused by the signal loss along the channel, increasing
with the frequency and distance between devices connected. Interferences and Noise,
having different causes whether in an indoor or outdoor environment. For indoor
communications, the main causes for interference and noise are the
equipments/appliances connected to the power line.
It is commonly accepted that five classes of noise are present in the power line:
colored background noise; narrow-band noise; periodic impulsive noise asynchronous
to the mains frequency; periodic impulsive noise synchronous to the mains frequency
and asynchronous impulsive noise. Although natural the appearance of any of the
above classes of noise, asynchronous impulsive noise raises from the switching on and
off of appliances connected to the network, causing severe system degradation.
The PLC channel model is far from being standardized, and there is no widely
accepted model as is the case with other communications environments, namely
telephone or mobile channels. Studies on this issue are based on measurements taken
directly from the network, or using the knowledge of topology and characteristics of
the network elements (wiring, cable type, distances, loads). These models will have a
specific scope, and are valid for the local network being used.
Models based on topology knowledge are available in the literature, e.g. [2-5]
but are considered as unfeasible to use in a general context due to the inherent need of
determining all the network parameters.
A power line model of the transfer function, based on extended measures was
given by Zimmermann and Dostert [6] in 2002, using multipath signal propagation,
with several paths and different delays and attenuations. The model is given as:
H (f ) =
N
∑
i =1
gi
N
weighting
factor
(
)
− a +a f k d
0
1
i
− j 2π f τ i
. e
. e
attenuation
factor
delay
factor
(1.3)
Where N is the number of paths between emitter and receiver; i is the path
number; a0 and a1 are attenuation parameters; k is factor typically varying between 0.5
and 1; gi is the weighting factor for path i; di is the length of path i; and τi is the delay
for path I ( τ i = di / v p , di is the length of path I and vp is the signal propagation
velocity).
The above model is obtained by analyzing a multipath signal propagation with
just one tap on the line, and then combined by superposition for the complete network.
The attenuation factor given was obtained as a simplification of the initial form
given in [6] by extensive analysis of real measured attenuation results.
Comparison results for this model where given in [6] and, although the
complexity inherent to the model is high (namely the numerous parameters needed to
estimate for an accurate matching of the channel model), it gives accurate results for a
large signal bandwidth. Fig. 1.20 shows the results for a measurement in a 110 meter
link containing 6 branches of about 15 meters, together with the simulated model
(N=44 in this case):
Although, for practical use, the model complexity is very high, it can be
simplified, reducing the total number of branches (N) still giving good results. In this
case, as N is reduced, the model will start to give poor agreement on the deep notches
present in the transfer function (see Fig. 1.21).
Fig. 1.20 – Model with 44 paths. (a) Amplitude response. (b) Phase details.
(c) Impulse response. (From [6]).
Fig. 1.21 – Model with 15 paths. (a) Amplitude response. (b) Phase details.
(c) Impulse response. (From [6]).
Task 1 References
[1] AMERICAN RADIO RELAY LEAGUE, “ARRL, the National Association for
Amateur Radio“(http://www.arrl.org)
[2] J. BARNES, “A physical multi-path model for power distribution network
propagation,” in Proc. 1998 Int. Symp. Powerline Communications and its
Applications, Tokyo, Japan, Mar. 1998.
[3] A. DALBY, “Signal transmission on powerlines – Analysis of powerline
circuits,” in Proc. 1997 Int. Symp. Powerline Communications and its
Applications, Essen, Germany, April 1997.
[4] H MENG, S. CHENG et al, “Modeling of Transfer Characteristics for the
Broadband Power Line Communication Channel,” IEEE Transactions on Power
Delivery, Vol. 19, No. 3, July 2004.
[5] S. GALLI, T. C. BANWELL, “A deterministic Frequency-Domain Model for the
Indoor Power Line Transfer Function,” IEEE Journal on Selected Areas in
Communications, Vol. 24, No. 7, July 2006.
[6] M. ZIMMERMAN, K. DOSTERT, “A Multipath Model for the Powerline
Channel,” IEEE Transactions on Communications, Vol. 50, No. 4, April 2002.
Task 2 – Comparative Study of Coding Schemes and Digital
Modulation Techniques (01-10-2005 to present)
To study and compare the different coding strategies that best suits the
communication over power lines.
Also, to compare the different digital modulation techniques that can be used to
modulate OFDM subcarriers.
2. Matlab Simulink Simulation of a MODEM for high speed
Power Line Communications with Error Correction Codes
The proposed power line communication (PLC) system simulation development
has continued. Synchronization at the receiver and other main blocks (as for instance
other type of channels and new equalizer) were added. More recently, some blocks
concerning correction codes were implemented. This process is still in the beginning,
and both Turbo codes and Low-Density Parity-Check (LDPC) codes are under
evaluation.
Since the PLC channel is a very noisy environment (usually a mix of
time-varying erasure and fading channels), the usual trade-off in decrease the error
rate is to increase transmission power or reduce data rate. Since these two standard
approaches run against the original goal of low-complexity hardware and high data
rates, another route must be taken.
Hence, in order to maintain data integrity across the PLC channel while
providing high data rates, it is essential to consider the use of error-correction coding
constructs. [See appendix A2.1 for a comparison of relevant ECC methods]. The
current (2006) most efficient ECC schemes used are Turbo Codes and Low Density
Parity Check codes (LDPC).
The following ECC's are scheduled to be implemented and tested: Low Density
Parity Check codes (LDPC) and Turbo Codes. See Appendix A2.1 for a quick
comparison.
2.1. Linear Block Codes
The structure of a linear block code is completely described by the generator matrix G or the
parity check matrix H. The capacity of correcting symbol errors in a codeword is determined by
the minimum distance (dmin).
For a (7,4) Hamming Code with generator matrix H
[
]
1 1 1 0 1 0 0
H= 1 1 0 1 0 1 0
1 0 1 1 0 0 1
dmin is the least number of columns in H that sum up to 0.
2.2 Low Density Parity Check
While LDPC [1], [2] and other error correcting codes cannot guarantee perfect
transmission, the probability of lost information can be made as small as desired. As of
2001 codes have been built within 0.0045 dB of the Shannon Limit [3].
As with other linear codes, a LDPC code is completely described by it's the
generator or parity check matrix, although LDPC matrices have special properties
such as
z H is sparse
c Very few 1’s in each row and column.
c Expected large minimum distance
z Regular LDPC codes
c H contains exactly Wc 1’s per column and exactly Wr=Wc(n=m) 1’s
per row, where Wc m.
z If the number of 1’s per column or row is not constant, the code is an irregular
LDPC code, which usually (with adequate construction) outperforms regular
LDPC codes.
The encoding, as with other linear block codes, can be described by the
relationship C=XG. Unfortunately, there are some issues with this algebraic
implementation such as G being very large (10000,5000), and not sparse (as opposed
to H). An alternative approach to simplified encoding is to design the LDPC code via
graph methods.
The general decoding of linear block codes follows the relationship CHT=0
only if C is a valid codeword. The used decode does not use this relationship, since its
full implementation is very inefficient. A sum-product algorithm and message passing
algorithm are being evaluated for decoding purposes
2.3. Methodology
For modelling the full ECC system, an incremental design philosophy was
chosen, and building upon previously achieved results. The following table shows the
channel and ECC combination matrix, and expected implementation complexity.
Channel
ECC
Class
Complexity
Class
Complexity
BER
low
regular LDPC
low
AWGN
low
irregular LDPC
high
BER+AWGN
moderate
turbo
moderate
PLC
moderate
turbo + interleaver
high
Table 2.1: List of expected channel and ECC's combinations (16) expected to be
tested.
Currently, the channels being modelled are BER and AWGN. The codes being
tested are regular LDPC, and irregular LDPC.
The current modelling architecture is shown in the next figure:
Fig. 2.1 Modeling architecture.
The original data (source block) is error-encoded and sent through the channel.
After an iterative decoding, in order to correct transmission errors, the data is
delivered to the receiver. An observer module (ECC performance evaluation)
monitors and signals error rates.
z The Channel block can be any of the following:
c Average White Gaussian Noise (AWGN)
c Binary Erasure (BER
c Power Line (PLC)
c any mix of the above channels
z The ECC encoder/decoders can be either be of following codes
c Low Density Parity Check
c Turbo Codes
z Modulator and Demodulator currently implement Binary Phase Shift Key
(BPSK), but future work will evaluate other modulation blocks.
2.4. Preliminary Results
The usual LDPC code is a regular one (i.e. all columns have the same weight).
It has been shown in [4] that irregular codes (with different weights per column) with
cycles removed, outperform regular ones. Cycles are a pattern or sequence of zeros or
ones (in the parity check matrix) that repeats itself in different columns. The existence
of cycles degrades the performance of the code. The following figure shows the
performance difference of regular code and code with all cycles of size 4 removed.
Fig. 2.2 - BER for regular and 4-cycle removed.
2.5. Conclusions and Short Term Work
The current work stage, is focused in the topmost four tasks of table 2, which
means the current effort is centred in LDPC codes. Some preliminary results show the
adequacy of LDPC codes as a effective choice for ECC.
As stated in the two previous sections, a more thorough comparison between
Turbo Codes and LDPC parameters will have to be carried out.
The following are a list of the (expected) remaining tasks:
Tasks
Reasoning
LDPC cycle removal
Assure current algorithm for cycle removal is optimal
LDPC parameters
Select appropriate LDPC parameters n, k, r for optimal code
performance
LDPC decoding algorithm
Must selected between MAP and sum-product decoding
LDPC + channel modeling
Must develop a larger test result bank, for AWGN and BER
channels
LDPC
modeling
PLC
channel Full suite of results for evaluation LDPC as selected ECC
Turbo code encoder/decoder
Create turbo encoder/decoder implementation
Modulation schemes
Test the overall performance of the system, while using
modulation schemes, other than BPSK
TC + PLC channel modeling Full suite of results for evaluation Turbo Codes as selected
ECC
Final data analysis, and end report
Table 2.2 - List of expected tasks.
Appendices
A2.1 ECC methods and features quick reference
A2.1.1 Turbo Codes
Pros:
z
z
close to approaching the Shannon limit
well research (since 1993)
Cons:
z
z
high encoding/decoding complexity
patent encumbered
A2.1.1 LDPC
Pros:
z
z
z
z
suitable parallel encoding/decoding
linear decoding complexity in time
lowest error rate floor (minimum distance is proportional to code
length)
as close as desired to Shannon limit
Cons:
z
z
cycles within the code internal structure degrade decoding performance
(see preliminary results)
“worst” than turbo codes for short code block lengths
A2.2 Timeline of significant ECC discoveries and events
1949
Claude E. Shannon publishes his landmark paper Communication in the Presence of
Noise, defining a bound on the maximum amount of error-free digital data (that is,
information) that can be transmitted over such a communication link with a
specified bandwidth in the presence of the noise interference, under the assumption
that the signal power is bounded and the Gaussian noise process is characterized by
a known power or power spectral density.
1950
Richard Hamming introduces Hamming codes for forward error correction (FEC - a
type of ECC whereby the sender adds redundant data to its messages), which allows
the receiver to detect and correct errors (within some bound) without the need to ask
the sender for additional data.
1955
Peter Elias introduces convolutional codes
1960
Irving S. Reed and Gustave Solomon propose Reed-Solomon codes
1960
Robert G. Gallager proposes Low-density parity-check codes; they are unused for
30 years due to technical limitations.
1967
Andrew Viterbi presents the Viterbi algorithm, making decoding of convolutional
codes practicable.
1993
Claude Berrou, Alain Glavieux and Punya Thitimajshima introduce Turbo codes
1998/9
Richardson, Urbanke, and MacKay, rediscover LDPC
Task 2 References
[1]
[2]
[3]
[4]
D. MACKAY, "Good Error-Correcting Codes Based on Very Sparse Matrices,"
IEEE Transactions on Information Theory, vol. 45, no. 2, March 1999
D. MACKAY, R.M. NEAL, “Near Shannon limit performance of low density
parity check codes”, Electronic Letters, vo1.32, No.18, pp.1645-1646, August
1996
SAE-YOUNG CHUNG, G. D. FORNEY, T. J. RICHARDSON and R.
URBANK, "On the Design of Low-Density Parity-Check Codes within 0.0045
dB of the Shannon Limit," IEEE Communications Letters, vol. 5, no. 2,
February 2001
J. MCGOWAN, R. WILIAMSON, "Removing Loops from LDPC Codes,"
Australian Communication Theory Workshop Proceedings, 2003
Task 3 – Adaptive Communication Techniques (01-10-2005 to 31-032007)
To compare the different adaptive OFDM techniques already available for
transmission over media other than power lines (for instance, bit rate reduction,
precoding, OFDM subcarrier supression), and assess their suitability for PLC
communication.
To develop new adaptive schemes that take in consideration the specific nature of the
power line transmission medium.
In this Task, adaptive techniques have been developed and added to the
communication system program developed in Task 2. A new equalizer, which
performs the crossing information of the noise channel between adjacent sub-bands
have been developed and tested. Also, a new adaptive algorithm - the Kalman LMS have been developed and tested.
3.1 The KLMS Algorithm and It Simplification SIKLMS
The Least Mean Squares (LMS) algorithm for adaptive filters has bean
extensively studied and tested in a broad range of applications [1–4]. In [1] and in [5]
a relation between the Recursive Least Squares (RLS) and the Kalman filter [6]
algorithm is determined, and in [1] the tracking convergence of the LMS, RLS and
extended RLS algorithms, based on the Kalman filter, are compared. However, there
is no link established between the Kalman filter and the LMS algorithm.
The classical adaptive filtering problem can be stated in the following manner.
Given an input signal u(n) and a desired signal d(n) determine the filter, w, that
minimizes the error, e(n), between the output of the filter, y(n), and the desired signal,
d(n). An algorithm that solves this problem is the well known LMS, which for the
case of Finite Impulse Response (FIR) Transversal filters, is given by,
w(n + 1) = w(n) + m u(n)* e(n)
(1)
This equation updates the vector of the filter coefficients w(n).The output of the
filter is y(n) = wT(n) u(n) with u(n) =[u(n)… u(n-N+1)] were N is the filter length, and
e(n) = d(n) - y(n).
It is known that the LMS algorithm is only stable if the step size is limited,
namely it should be inversely proportional to the power of the reference signal [1].
This leads to the normalized LMS algorithm (NLMS). It is shown in [1] that this
algorithm is stable as long as the step size a be restricted to 0 <a < 2 and of course,
u(n)T u(n)* ≠0. In order to prevent this last possibility, in practice, the algorithm is
usually modified to
w(n + 1) = w(n) + α
u (n)* e(n)
uT (n) u (n)* + q
(2)
where q is selected to be small enough when compared with uT(n) u(n)*. This is
usually chosen in an ad doc fashion. Techniques to select this value based on the
proposed algorithm are presented later.
The Kalman filter can be used in adaptive filtering by making a number of
correspondences. The adaptive filtering problem is reformulated as a state estimation
problem, were the state vector corresponds to the filter coefficients vector. Since the
state estimate is the state that minimizes the square of the error at each coefficient, it
will also minimize the output error of the filter [6]. The optimal filter variation in time
is modeled as a Markov model with white noise input, n(n), and state transition
matrix, F(n) = λI with λ close to one. The measured signal d(n) is related to the state
through the reference signal vector u(n) plus an additional measurement noise v(n).
The resulting algorithm is then,
α (n) = d (n) − uT (n) w(n)
w(n + 1) = w(n) + λ
∑ w (n + 1) = λ 2 ∑ w (n) − λ 2
(3)
∑ w (n)u (n)α (n)
u (n) ∑ w (n)u (n) + qv (n)
T
∑ w (n)u (n)uT (n) ∑ w (n)
+ Qnn (n)
uT (n) ∑ w (n)u (n) + qv (n)
(4)
(5)
The variance matrix ∑ w (n) can be made diagonal by carefully selecting the state
noise autocorrelation matrix Qnn(n) at each iteration. More, this can be done without
changing the state noise total power, tr{Qnn(n)}, were tr{} stands for the trace of the
matrix. To do this one simply makes ∑ w (n) = σ w2 (n) I and tr{Qnn(n)} = N qn(n) and
apply the trace operator to (5). The resulting algorithm is the Kalman based LMS
algorithm (KLMS) and is represented in table 3.1. Note that tr{u(n) uT(n)}= uT(n)u(n).
The actual algorithm presented in table 3.1 has been modified to allow complex
signals. Namely, in the calculation of the power and in the coefficients update, u(n)*,
the conjugate of u(n), is used in its place.
Initialize
w(0)=0
σ w2 (0) = σ w2 0
(6)
(7)
Iterate from n=0 to …
P=uT(n)u(n)*
(8)
α(n)=d(n)-uT(n)w(n)
(9)
w(n + 1) = w(n) +

σ w2 (n + 1) = σ w2 (n) 1 −

u (n)*α (n)
P(n) + qv (n) / σ w2 (n)
(10)

P ( n) / N
 + qn (n)
2
P (n) + qv (n) / σ w (n) 
(11)
Table 3.1 - Normalized LMS algorithm based on the Kalman filter - KLMS
algorithm.
The model for the state variation is,
w j (n + 1) = λ w j (n) + n j (n)
(12)
Each coefficient corresponds to a low frequency signal, with time constant given
by τ = T / ln(λ) were T is the sampling period. This can be approximated by τ = T /(1
- λ) if λ is close to one. So one has, λ ≈ (1-T/τ). The variance of each coefficient is
easily calculated as,
σ w2 =
qn
1− λ2
(13)
This should be equal to the value chosen to initialize the algorithm σ w2 = σ w2 0 .
This results that the state noise can be chosen as,
qn = σ w2 0 (1 − λ 2) ≈ 2σ w2 0
T
(14)
τ
where the last approximation is valid for large τ , where τ is the time constant of the
underlaying model, as previously discussed.
The use of the NLMS algorithm can lead to amplification of the measurement
noise in low order filters when the reference signal power takes low values. This can
be seen by assuming d(n) = uT(n)wop(n) + v(n) and rearranging the NLMS algorithm
to,
w(n + 1) = ( I − Γ) w(n) + Γwop (n) +
v ( n)
u (n)u* (n) + q
T
(15)
where Γ is a matrix given
Γ =α
u* (n)uT (n)
uT (n)u* (n) + q
(16)
Equation (15) may be made diagonal to represent a bank of lowpass first order
IIR filters with added noise, the last term in the equation. For low reference signal
power this term will assume high values, resulting in poor performance of the
algorithm. The KLMS solves this problem by carefully selection of the value of q.
Simulation results are presented for the case of a one coefficient complex filter
and a ten real coefficient filter. Comparisons are made with the LMS and NLMS
algorithm. The one-coefficient complex filter is typically used in orthogonal frequency
division multiplexing (OFDM) [7] channel equalization. In this application
equalization is done in the frequency domain resulting in one-coefficient filters. Also,
due to the presence of nulls in the channel frequency response and due to the low pass
characteristics of many channels, the input signal power varies considerably.
The measurement noise, which is a prior to the algorithm, can be considered
constant, resulting in a large variation of the signal-to-noise ratio. This fits nicely to
the KLMS formulation while the NLMS is more suitable for a fixed signal to noise
ratio, since the α parameter is related to it. Also, the NLMS will perform poorly when
the input signal power takes low values, as shown in the simulations.
1.2
Kalman LMS
NLMS
LMS
Mean Square Error
1
0.8
0.6
0.4
0.2
0
20
40
60
Iterations
80
100
Fig. 3.1 - Mean Square error convergence of the KLMS, NLMS and LMS
algorithm. The parameters off all the algorithms were optimized for best
performance
Fig. 3.1 presents the convergence curves of the mean square error between the
output of the adaptive filter and the desired signal for the case of a one coefficient
complex filter. The reference signal was uniform distributed with power of one, and
the measurement error had a standard deviation or root mean square value (RMS) of
0.3. This results in a signal to noise ratio of 10.4 dB that is enough to allow fairly low
bit error rate in QPSK communication. The measurement noise power of the KLMS
has set to, qv = (0.3)2, the optimal value, and the state noise to zero. The step size of
the LMS and NLMS were optimized to achieve a similar residual noise. The curves
are the result of the ensemble average of 100 trials.
It can be seen that the KLMS has the best performance. In the case of the
NLMS, due to the low filter order, occasional low values of the reference signal power
result in very high values of the residual error. The LMS has slower initial
convergence.
1.2
Kalman LMS
NLMS
LMS
Mean Square Error
1
0.8
0.6
0.4
0.2
0
20
40
60
Iterations
80
100
Fig. 3.2. Mean Square error convergence of the KLMS, NLMS and LMS
algorithm, with a 3 times higher reference signal level than in Fig. 1 but with the
same algorithms parameters.
In Fig. 3.2 the reference signal level was amplified three times, while the
parameters of all the algorithms were kept constant. It can be seen that the LMS
algorithm gets unstable. The NLMS has fewer problems, but it still suffers from
measurement noise amplification occasionally. The KLMS still performs accurately.
In addition, the KLMS has faster convergence than the NLMS.
Fig. 3.3 provides a comparison of the convergence of the mean square error of
the KLMS, and NLMS.
Kalman LMS
NLMS
Mean Square Error
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
20
40
60
Iterations
80
100
Fig. 3.3. Mean Square error convergence of the KLMS, NLMS and LMS
algorithm, for a 10 real coefficient filter.
The desired signal was equal to the reference signal filtered by a sinusoidal
bandpass filter, with unit gain at the center frequency. The reference signal had unit
power and the RMS of the measurement error was 0.3. Some care had to be taken in
the initial stages, when the filter buffer was not full. The NLMS buffer was initially
filled with ones to prevent the step size to increase to much at the initial stages. In the
case of the KLMS the buffer can be left at zero, as long as care is taken in choosing
the prior standard deviation of the filter coefficient, σ w2 0 . Both algorithms have similar
performance.
Simplification of the Algorithm
If one is not interested in the initial convergence, then the algorithm in Table 3.1
can be simplified. The coefficients estimation error standard deviation σ w2 (n)
converges to a steady state value, resulting that qv(n)/ σ w2 (n) converges to,
qv (∞) / σ w2 (∞) =
4qv
P
( −1 + 1 +
)
2
NPqn
(3.17)
This can be used in place of qv ( n) / σ w2 (n) . The value of the state noise can be
calculated as in (3.14).
Another approximation can be made if, the state noise is low or zero. In this case
equation 3.5 can be written as,
Σ −w1 (n + 1) = Σ −w1 (n) +
u (n)uT (n)
qv
(3.18)
The matrix Σ −w1 ( n + 1) can be approximated by a diagonal matrix if the reference
signal autocorrelation is narrow. Doing this and applying the trace operator results,
σ w−2 (n + 1) = σ w−2 (n) +
P ( n)
Nqv (n)
(3.19)
by defining the total power up to (but not counting) time n, PT (n) , by the equation,
PT (n + 1) = PT (n) + P(n)
(3.20)
one can prove by finite induction that
σ w−2 (n) =
PT (n) + X
Nqv
(3.21)
as long as
X = Nqv / σ w2 0 and PT (0) = 0
(3.22)
resulting in the algorithm presented in Table 3.2. Note that this algorithm is equivalent
to the KLMS for the case N = 1.
Initialize
w(0)=0
PT (0) =0
(3.23)
(3.24)
Iterate from n=0 to …
P=uH(n)u(n)
(3.25)
α(n)=d(n)-uT(n)w(n)
(3.26)
w(n + 1) = w(n) +
u (n)*α (n)
P (n) + PT (n) / N + qv (n) / σ w2 0
PT(n+1)=PT(n)+P(n)
(3.27)
(3.28)
Table 3.2 - Information Form Kalman Based LMS - IKLMS - algorithm
The algorithm also suggests further simplification where the time varying
quantity PT(n+1) is replaced by an estimate of its value at time M, resulting in,
w(n + 1) = w(n) +
u (n)*α (n)
 N + M −1 
H
2

 u (n) u (n) + qv / σ w0
N


(3.29)
We call this algorithm the Simplified Information Form Kalman LMS SIKLMS.
In the next simulation results, the reference signal is the output of the channel
and the desired signal is the input of the channel. The input of the channel was a
QAM64 signal with a power of one. A noise signal with standard deviation of 0.25
was added at the output of the channel. This means that the channel is driven with a
capacity gap of 3 dB. The measurement noise power of the KLMS has set to, qv =
(0.25)2, the optimal value. The step size of the LMS and NLMS and the N of the
SIKLMS were optimized to maximize the convergence rate of the algorithms,
resulting in the values of 0.5, 0.5 and 2.0. The curves are the result of the ensemble
average of 100 trials.
Fig. 3.4 presents the convergence curves of the mean square error between the
output of the adaptive filter and the desired signal for the case of a one coefficient
complex filter for channel equalization and tracking.
The step of the NLMS and LMS algorithm was set to 0.5 and the M parameter
of the SIKLMS was set to 2.0. It can be seen that the KLMS has the best performance.
In the case of the NLMS, due to the low filter order, occasional low values of the
reference signal power result in very high values of the residual error. The LMS and
SIKLMS both have good results.
Fig. 3.4. Mean-square error convergence of the NLMS, KLMS and
SIKLMS algorithms. The parameters of the LMS and NLMS were optimized for
maximum convergence.
In Fig. 3.5, the reference signal level was amplified by 40%, while the
parameters of all the algorithms were kept constant. It can be seen that the LMS
algorithm gets unstable. The NLMS has fewer problems, but it still suffers from
measurement noise amplification occasionally. The KLMS and SIKLMS still give
good results.
To note that in the conditions of Figures 3.4 and 3.5, namely N=1, the IKLMS
results in the KLMS.
Fig. 3.5. Mean Square error convergence of the LMS, NLMS, KLMS and
SIKLMS algorithms, with a 3 times higher reference signal level than in Fig. 3.4
but with the same algorithms parameters.
Fig. 3.6 provides a comparison of the convergence of the mean square error of
the IKLMS, Kalman Filter, KLMS, and NLMS for a 10 real coefficient filter. The
desired signal was equal to the reference signal filtered by a bandpass filter, with unit
gain at the center frequency. The reference signal had unit power and the RMS of the
measurement error was 0.03. The adaptive algorithms were only started after ten
iterations, when the input buffer was full. The step size of the NLMS was optimized
for best performance while in the KLMS, the algorithm’s parameters were chosen
naturally. As one can see, the performance of the Kalman filter is the best, but at the
expenses of a much heavier computational effort. All the others have a similar
performance. The SIKLMS, although not shown in this figure, present a behavior
similar to that of the KLMS.
As a conclusion, new versions of the NLMS algorithm based on the Kalman
filter (the KLMS, the IKLMS and the SIKLMS) were derived. The new algorithms are
stable since they were derived from the Kalman filter. They allows faster convergence
and much higher noise immunity when the reference signal vector norm takes low
values, namely in the case of low order filters (like in OFDM systems). In the NLMS
algorithm, q, prevents division by zero. In the new algorithms accurate formulas for q
give it good noise immunity properties. The simplified versions of the KLMS, namely
the IKLMS and the SIKLMS, although provide a slightly worse performance as the
original KLMS, they require a lighter computational effort, being good performancecomplexity compromises.
Root Mean Square Error
KLMS
IKLMS
NLMS
Kalman Filter
0.5
0.4
0.3
0.2
0.1
0
10
20
30
Iterations
40
50
Fig. 3.6. Mean Square error convergence of the Kalman Filter, KLMS,
IKLMS and NLMS algorithm, for a 10 real coefficient filter. The NLMS step was
hand optimized.
From the results obtained with this Task two papers have been submitted: one to
the ISCASSP'07 [8] and other to the ISCAS´07 [9].
3.2 The Crossing Information Adaptive Equalizer
The PLC channel is a time-variable response channel, susceptible to high noise
levels, due to the very different kinds of loads connected to the power grid. The model
used was proposed by Gotz, Rapp and Dostert [10]. Figures 3.7, 3.8 and 3.9 show its
amplitude response, phase response and impulse response, respectively.
The full system, simulated in MATLAB Simulink, has the architecture
represented in Fig. 3.10. From left to right, (top to bottom), the data in the system
flows from a random data source, arrives at the transmitter modem, where it is
encoded, modulated and sent through the PLC channel. At the receiver modem, after
demodulation and decoding the data is recovered. The remaining bottom blocks
implement performance monitoring.
Modulus (dB)
Phase (rad)
Fig. 3.7. PLC channel amplitude response.
Fig. 3.8. PLC channel phase response.
Amplitude
Fig. 3.9. PLC channel impulse response.
A more detailed functional block-level representation is presented in Fig 3.11.
Fig. 3.11. PLC system block-level architecture.
Simulation Results
Two of the constraints that were expected to greatly impact the outcome system
performance were channel equalization, and frequency offset between the transmitter
and receiver.
Channel equalization allows the receiver to compensate for some attenuation in
specific frequencies PLC channel, effectively trying to invert the PLC channel timevarying transfer function.
Three different simulations results for channel equalization are shown in Fig.
3.12. Blue line depicts the results for no-equalizer and no-PLC channel scenario. Red
line depicts the results for equalizer without PLC channel scenario. Finally, green line
depicts the results for equalizer and PLC channel scenario.
For both no-PLC channel scenarios, the symbol probability error is always lower
when the equalizer is used. Both lines converge to probability 0.75, which is the
intrinsic system symbol probability error, for very high noise levels. For the PLC
channel scenario and since the line noise is larger, the equalization process
convergence is worst, and the symbol probability error is higher.
Frequency offset between transmitter and receiver can cause degradation in the
symbol decoding process and in severe cases no synchronization between transmitter
and receiver. Figures 3.13 and 3.14 depict two different scenarios, with probability of
symbol error (symbol error rate) of 10-2 and 10-4, respectively. The offset (X axis) is
measured in symbols length. The type of channel used is AWGN. An important detail
from both figures, is that they both show a bias (static error), when compared to the
ideal channel (Fig. 3.13).
OFDM carrier frequency desviation
Fig. 3.12. Performance evaluation of the equalizer.
Fig. 3.13. Symbol error rate with ideal channel.
Fig. 3.14. Performance evaluation for a symbol error rate of 10-2.
Fig. 3.15. Performance evaluation for a symbol error rate of 10-4.
From both figures, one can conclude that there must be a correlation between
high frequency offsets and high SNRs at the channel, in order to have low probability
of symbol error.
As a conclusion, according to the so far obtained results in the OFDM simulated
PLC system, the following recommendations were confirmed:
z
It would be advantageous to implement an adaptive OFDM control in the
transmitter to detect and avoid the channel frequencies that lead to more errors, in
order to reduce the error probability of the transmitted signal;
z
Some sort of forward error correction (FEC) coding should be
implemented, in order to attempt extracting the most possible information of a
received sequence, instead of just discarding it, with the added benefit of increasing
the transmission bit rate.
Task 3 References
[1]
[2]
S. HAYKIN, Adaptive Filter Theory. Prentice-Hall, Inc., 1996.
J. HOMER, “Quantifying the convergence speed of LMS adaptive FIR filter
with autoregressive inputs,” Electronics Letters, vol. 36, no. 6, pp. 585–586,
March 2000.
[3] Y. GU, K. TANG, H. CUI, and W. DU, “Modifier formula on mean square
convergence of LMS algorithm,” Electronics Letters, vol. 38, no. 19, pp.1147 –
1148, September 2002.
[4] M. CHAKRABORTY and H. SAKAI, “Convergence analysis of a complex
LMS algorithm with tonal reference signals,” IEEE Trans. Speech Audio
Process., vol. 13, no. 2, pp. 286 – 292, March 2005.
[5] A. SAYED and T. KAILATH, “A state-space approach to adaptive RLS
filtering,” IEEE Signal Process. Mag., vol. 11, no. 3, pp. 18 – 60, July 1994.
[6] B. D. O. ANDERSON, Optimal Filtering. Dover Publications, 2005.
[7
J. A. C. BINGHAM, “Multicarrier modulation for data transmission: an idea
whose time has come,” IEEE Commun. Mag., vol. 28, no. 5, pp. 5–14, May
1990.
[8] P. LOPES, G. TAVARES, J. GERALD, “A New Type of Normalized LMS
Algorithm Based on the Kalman Filter”, ICASSP’07.
[9] P. LOPES, J. GERALD, “New Normalized LMS Algorithms Based on the
Kalman Filter”, ISCAS’07.
[10] M. GOTZ, M RAPP and K. DOSTERT, “Power Line Channel Characteristics
and Their Effect on Communication System Design”, IEEE Communications
Magazine, pp. 0163-6804, Apr. 2004;
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