Presentation - Lehrstuhl für Elektronische Bauelemente

Transcrição

SILICON TECHNOLOGY
Heiner Ryssel
Fraunhofer-Institut für Integrierte Systeme
und Bauelementetechnologie (IISB)
(Fraunhofer Institute of Integrated Systems and Device Technology)
Schottkystrasse 10, 91058 Erlangen
and
Universität Erlangen-Nürnberg, Lehrstuhl für Elektronische Bauelemente
(University Erlangen-Nuremberg, Chair of Electron Devices)
Cauerstrasse 6, 91058 Erlangen
Indo - German Winter Academy 2008
December 13 -19, 2008, Chennai, India
Stand 11.12.2007
Lehrstuhl
Elektronische Bauelemente
Universität
Erlangen-Nürnberg
Fraunhofer Inst. Integr. Systeme &
Bauelementetechnologie
1
Silicon Technology











Introduction
Crystal Pulling and Wafering
Cleanroom
Cleaning
Oxidation
Layer Deposition
Lithography
Etching
Diffusion
Ion Implantation
Assembly and Packaging
Lehrstuhl
Universität
Erlangen-Nürnberg
2
Silicon Technology











Introduction
Cleanroom
Cleaning
Oxidation
Layer Deposition
Lithography
Etching
Diffusion
Ion Implantation
Lehrstuhl
Universität
Erlangen-Nürnberg
3
Silicon Technology - Introduction
 Schematic View of Integrated Circuit Fabrication
Front End fabrication
takes place in a clean room
Lehrstuhl
Universität
Erlangen-Nürnberg
4
Silicon Technology











Introduction
Cleanroom
Cleaning
Oxidation
Layer Deposition
Lithography
Etching
Diffusion
Ion Implantation
Lehrstuhl
Universität
Erlangen-Nürnberg
5
 Production of Ultra Pure Silicon
– Production of metallurgic silicon from quartz sand by reduction with
carbon (1500-2000 °C)
– Production of a halogen compound (SiHCl3) of silicon (350 °C)
– Purification by distillation
– Poly crystal by pyrolysis (7-15 days at 1100 °C)
– Crystal growth by the Czochralski method (CZ method, 5-24 hours at
1415 °C)
– Doping during crystal growth
– Alternative methods exist, but have less importance
Lehrstuhl
Universität
Erlangen-Nürnberg
6
 Crystal Growth by the CZ Method
Three important steps in
crystal growth
Lehrstuhl
Universität
Erlangen-Nürnberg
7
 Sawing with Inner Diameter Saw
– Standard saw for wafer diameters up to 200 mm
– Sectioning of the rods for subsequent wire sawing
Lehrstuhl
Universität
Erlangen-Nürnberg
8
 Sawing with Wire Saw
– Most modern sawing method
– Standard method for diameters 300 mm and larger
Lehrstuhl
Universität
Erlangen-Nürnberg
9
 Polishing of the Wafer Surface
Lehrstuhl
Universität
Erlangen-Nürnberg
10
Overview of Silicon Technology











Introduction
Cleanroom
Cleaning
Oxidation
Layer Deposition
Lithography
Etching
Diffusion
Ion Implantation
Lehrstuhl
Universität
Erlangen-Nürnberg
11
Cleanroom
 Schematic Cross Section of the LEB Cleanroom
Ventilation unit
Plenum
Cleanroom class 100
Recirculation
Media basement
Cross section of the LEB cleanroom
Lehrstuhl
Universität
Erlangen-Nürnberg
12
Cleanroom
 Cleanroom Classes
-
1000 1000 particles* per cubic foot
100
100 particles* per cubic foot
10
1
(105-106 external air)
*particles >0,5µm in diameter
Cleanroom at Intel 1968
approx. class 10000
Cleanroom at Intel 1990
approx. class 1
Lehrstuhl
Universität
Erlangen-Nürnberg
13











Introduction
Cleanroom
Cleaning
Oxidation
Layer Deposition
Lithography
Etching
Diffusion
Ion Implantation
Lehrstuhl
Universität
Erlangen-Nürnberg
14
Cleaning
 Cleaning steps are carried out between numerous processing
steps in order to avoid defects by impurities
 Impurities (Contamination) may be:
–
–
–
–
Particles
Organic impurities
Metallic impurities
Natural oxide
 Impurities lead to:
–
–
–
–
Oxide defects
Short circuits/breaks of conducting lines
Shift of threshold voltage
In general:
defect or malfunctioning devices
Lehrstuhl
Universität
Erlangen-Nürnberg
15
Cleaning
 Cleaning Methods (Examples)
– Wet-chemical cleaning sequence
•
•
•
•
•
•
Caro: 1H2O2+2H2SO4
Rinsing with H2O
SC-1: 1H2O2+1NH4OH + 5H2O
SC-2: 1H2O2+1HCl+6H2O
Rinsing with H2O
Drying (Spin-drying, Marangoni)
– Dry-chemical cleaning method
Single wafer etcher by SEZ
• HCl (> 1000°C)
• HF/Methanol vapor
• Ar/H2 plasma
Lehrstuhl
Universität
Erlangen-Nürnberg
16
Cleaning
 Purity Standards of Silicon Wafers, 180 nm Technology
Object
Property
Hypothetical Si wafer
Lehrstuhl
Hypothetical
Wafer
Silicon
Wafer
Diameter
12900 km
(Earth)
300 mm
Thickness
38 km
875 µm
Comparison
1 small marble
(1.2 cm)
1 surface atom
(1Å)
Purity
standard
( crit. metals)
1 marble/14 m2
1.3·1010 at/cm2
Universität
Erlangen-Nürnberg
17
Silicon Technology











Introduction
Cleanroom
Cleaning
Oxidation
Layer Deposition
Lithography
Etching
Diffusion
Ion Implantation
Lehrstuhl
Universität
Erlangen-Nürnberg
18
Oxidation
 Oxidation is the core process of silicon planar technology. Due
to the excellent properties of SiO2 it serves for
Ions
– Masking
Thick oxide
(diffusion, implantation)
Implanted ions
– Insulation
(metallic conducting lines)
Thick oxide
Thick oxide
– Control
(gate oxide)
– Passivation
Thick oxide
(CVD)
(layer deposition)
Thin oxide
Lehrstuhl
Universität
Erlangen-Nürnberg
19
Oxidation
 The Principle of Oxidation
– Oxygen (dry oxidation) or water vapor
(wet oxidation) are blown over the silicon
wafers in a heated quartz tube
– Wet oxides are thicker than dry oxides
at the same time and temperature
– Reaction equations
• dry: Si + O2  SiO2
• wet: Si + 2H2O  SiO2 + 2H2
• T = 800-1250°C
• t = 30 min - 18 h
Wafers being inserted into the
oxidation tube
Lehrstuhl
Universität
Erlangen-Nürnberg
20
Oxidation
 Oxidation Furnace
– Resistance heated quartz tubes (SiO2), horizontal or vertical
– Gases directly injected or provided by combustion (H2+O2) or bubblers
Together with
metals (impurities),
chlorine forms
volatile compounds
4-section oxidation furnace
Sketch of an oxidation tube
Lehrstuhl
Universität
Erlangen-Nürnberg
21
Oxidation
 Local Oxidation (LOCOS, LOCal Oxidation of Silicon)
Oxidation
SiO2
(approx. 50 nm)
– Advantages:
• Reduction of unwanted capacities
outside active areas
• Relatively plane suface of oxidized wafers
Nitride deposition
Si3N4
(approx. 250 nm)
Photo technology
– Disadvantages:
• lateral oxidation below nitride
• maybe defects by stress
Thick oxide
wet oxidation
– Alternative:
• STI (shallow trench isolation)
Lehrstuhl
Universität
Erlangen-Nürnberg
Nitride and oxide etching
22











Introduction
Cleanroom
Cleaning
Oxidation
Layer Deposition
Lithography
Etching
Diffusion
Ion Implantation
Lehrstuhl
Universität
Erlangen-Nürnberg
23
Layer Deposition
 Besides thermal oxides, numerous other - both insulating and
conducting - layers are needed, which are produced by
different methods
 Layers are needed for:
– Masking for
• Oxidation (LOCOS)
• Diffusion
• Ion implantation
• Etching
– Insulation
– Electrode (gate)
– Contact (silicides, metals)
– Diffusion Barriers (against intrusion of metals)
– Passivation (against corrosion from outside)
Lehrstuhl
Universität
Erlangen-Nürnberg
24
Layer Deposition
 Chemical Vapor Deposition (CVD)
Principle: Deposition of solid
layers by chemical reaction of
gases containing components
of the layers.
Pressure: atmospheric (APCVD)
or (in most cases) low pressure
(LPCVD)
Temperature: 400-600 °C
Layers: Single-crystalline
silicon (epitaxy), polysilicon,
SiO2, Si3N4, glasses,
tungsten, aluminum, copper
Lehrstuhl
Universität
Erlangen-Nürnberg
25
Layer Deposition
 Chemical Vapor Deposition (CVD)
– Examples
Layer
Reaction Equations
Temperature (°C)
SiO2 : LTO
SiO2 : TEOS
SiO2 : HTO
SiH4+O2 SiO2+H2
Si(OC2H5)4  SiO2+gas. react.products
SiCl2H2+N2O  SiO2+2N2+2HCl
SiH4+CO2+H2  SiO2+gas. RP
400-450
650-700
850-900
850-950
Glasses
Addition of PH3, AsH3, B2H6
Si3N4
3SiH2Cl2+4NH3  Si3N4+6HCl+6H2
700-900
Poly-silicon
SiH4  Si+2H2
600-650
Tungsten: selective
Tungsten: all over
2WF6+3Si  2W+3SiF4
WF6+SiH4  W+SiF4+2HF+H2
300
400-450
Lehrstuhl
Universität
Erlangen-Nürnberg
26
Layer Deposition
 Epitaxy
Variant of the CVD method, for growing single-crystalline layers
– Starting substances: SiH4, SiH2Cl2, SiHCl3, SiCl4
– Reaction equation (example): SiCl4+2H2  Si+4HCl
– Doping: by injection of suitable gases, e.g. AsH3, PH3, B2H6
– Reactor types: Barrel (left), Pancake (right)
Gas inlet
Gas inlet
Quartz lamps
Wafers
Wafers
HF coils
Outlet
Outlet
Lehrstuhl
Graphite
mount
Universität
Erlangen-Nürnberg
Gas inlet
27
Layer Deposition
 Sputtering (PVD)
Metals, silicides, diffusion barriers are generally
deposited by sputtering
– Principle:
• Between two parallel electrodes
a (DC) voltage is applied at
reduced pressure
• from the resulting glow
discharge ions (normally
argon) are accelerated to
the metal cathode,
• these strike out atoms,
• the atoms are deposited
on the silicon wafer
Lehrstuhl
Universität
Erlangen-Nürnberg
28
Layer Deposition
 Sputtering (PVD): Typical Sputtered Layers
– AlSiCu: Al with 1% Si and 0,5 % Cu
• Si admixing, in order to avoid „spiking“
• Cu admixing, in order to reduce „electromigration“
– TiN: Titanium is reactively sputtered in N2
• TiN works as a diffusion barrier against „spiking“
– TiSi2, TaSi2, MoSi2, CoSi2
• Silicides must be tempered to
low resistance phases
Lehrstuhl
Universität
Erlangen-Nürnberg
29
Layer Deposition
 Spin-On
– Dielectric layers (SiO2, glasses, polymers)
are spinned on as an intermediate insulation
or as a diffusion source, just like resist
(refer to chapter on lithography)
 Electroplating
– Copper is getting more and more
important for metallization.
– Today it is deposited by
electroplating
Lehrstuhl
Universität
Erlangen-Nürnberg
30
Silicon Technology











Introduction
Cleanroom
Cleaning
Oxidation
Layer Deposition
Lithography
Etching
Diffusion
Ion Implantation
Lehrstuhl
Universität
Erlangen-Nürnberg
31
Lithography
 Patterning of the respective layers is
done by lithography and subsequent
etching
 Principle
– A thin layer of photoresist is spun onto the
wafer surface.
– Photoresist is pre-baked at 120°C
(to drive out the solvents)
– and is exposed using a photomask
or a direct writing technique.
– Finally, the resist is developped.
During development, the exposed
(positive resist) or non-exposed
(negative resist) will be dissolved.
– Using the resist as a mask, the layer
will be etched.
Lehrstuhl
Universität
Erlangen-Nürnberg
32
Lithography
 Photo Resists
– Positive resist is soluble after exposure
– Negative resist is insoluble after exposure
– Typical resists: Novolack (positive), PMMA
Photo resist
Layer
Substrate
Negative resist
Positive resist
Development
Etching
Resist stripping
Lehrstuhl
Universität
Erlangen-Nürnberg
33
Lithography
 Exposure Techniques
–
–
–
–
–
Contact Printing
Contact Printing
Proximity Printing
Proximity Printing
Projection Exposure
Light Source
Writing
Limitiations
Projection Exposure
• Diffraction
• Photo resists
Mask
Substrate+
Photo resist
Proximity
gap
Lehrstuhl
Universität
Erlangen-Nürnberg
34
Lithography
– Optical projection imaging
• Wavelength
Mercury-vapor lamp: 436 nm (g-Line), 365 nm (i-Line),
Excimer laser: 248 nm (KrF), 193nm (ArF), 157 nm (F2)
Plasma: 10-15nm
• Resolution limit
x  k1

NA
NA: Numerical aperture
of projection lens
• Depth resolution
f  k 2

NA2
Lehrstuhl
Universität
Erlangen-Nürnberg
35
Lithography
 Planarization: Chemo-Mechanical Polishing (CMP)
– Due to limited depth of focus of lithography, a planarization of the
topography is necessary for integrated circuits with minimal
dimensions below aprox. 200 nm
Lehrstuhl
Universität
Erlangen-Nürnberg
36
Lithography
– Electron beam exposure
electron source
Wehnelt cylinder
• De Broglie-wavelength

h
m v
-10...-50 kV
Anode
capacitor plates for
beam fade-out
aperture
• Resolution ist limited by
electron and secondary
electron backscattering
magnetic lens
electron beam
Deflection coils
aperture
"
magnetic lense
detector
substrate
laser controlled table
Lehrstuhl
Universität
Erlangen-Nürnberg
37
Silicon Technology











Introduction
Cleanroom
Cleaning
Oxidation
Layer Deposition
Lithography
Etching
Diffusion
Ion Implantation
Lehrstuhl
Universität
Erlangen-Nürnberg
38
Etching
 Pattern transfer is done by wet or dry etching.
 Photo resist or a layer which is not affected by the etching
process can be used as masking material.
anisotropic
Process steps
• before etching
layer
isotropic
photo resist
substrate
• after etching
• after mask removal
Lehrstuhl
Universität
Erlangen-Nürnberg
39
Etching
 Wet Chemical Etching
–
–
–
–
–
Wet chemical etching is usually isotropic
Isotropic etching resulting in lateral undercut
Etching solvents are highly selective
(ratio of etch rates > 100 : 1)
Wet etching is simple and cheap
Photoresists or other layers which are
resistant against the etchants can be used
as masks
Wet etching bench for 300mm wafers
Lehrstuhl
Universität
Erlangen-Nürnberg
40
Etching
 Wet Chemical Etching: Etchants (liquid)
Layer
Mask
Etchant
SiO2
Photo resist
HF (1-5%)
BHF: 12,5% HF (50%) + 87,5% NH4F (40%)
Si3N4
SiO2
H3PO4 (86%)
Polysilicon
Photo resist
99% HNO3 (50%) + 1% HF (50%)
Aluminum
Photo resist
75% H3PO4 + 5% HNO3
Titanium
Photo resist
HF (1%)
TiSi2, TaSi2
Photo resist
BHF
Lehrstuhl
Universität
Erlangen-Nürnberg
41
Etching
 Dry Etching
– Dry etching is performed in a barrel reactor or, more often, in a
parallel plate reactor
– Dry etching in general is isotropic
– Photo resist is used for masking.
Lehrstuhl
Universität
Erlangen-Nürnberg
42
Etching
 Dry Etching: Etchants (gaseous)
Material
Etchant
Comment
Si Trench
Etching
SF6 /O2 (etching), C4F8 (passivation)
Multi-step-process,
Switching: etch./passivation
Polysilicon
Cl2 (etching), HBr, O2 (passivation)
Multi-step-process
SiO2
CF4, C4F8 (etching), CHF3, C2F6
(passivation)
Si3N4
SF6, CF4,(etching) CHF3
(passivation)
SF6: low etch rate for SiO2
CF4: low etch rate for Si
Al, AlSi(1%)Cu,
AlCu(2%)
BCl3,(aluminum oxide etching), Cl2
(etching), BCl3, CCl4 (passivation),
Cl residue removal with CF4, CHF3,
SF6 or wet chemically with H2O
Multi-step-process (Al2O3
etching, Al etching, pass.),
Cl residue removal for
prevention of corrosion
W
SF6 (etching), CHF3, N2 (pass.)
WSi2
C2F6/Cl2/O2
TiN
C2F6/O2
Lehrstuhl
Universität
Erlangen-Nürnberg
43
Silicon Technology











Introduction
Cleanroom
Cleaning
Oxidation
Layer Deposition
Lithography
Etching
Diffusion
Ion Implantation
Lehrstuhl
Universität
Erlangen-Nürnberg
44
Diffusion
 n- and p-Doping is necessary for manufacturing electron
devices. Diffusion has been applied widely in the early
days of silicon processing.
 Principle
– at elevated temperatures (800 - 1200°C) doping atoms diffuse into
silicon
– Same equipment as for thermal oxidation
– p-doping: boron, indium, (gallium, aluminum)
– n-doping: phosphorus, antimony, (arsenic)
 Techniques
– Diffusion from a unlimited source (z.B. B2H6, POCl3, gaseous)
– Diffusion from limited source (e.g. from a previously deposited
borosilicate layer)
– Predeposition and drive-in
– Predeposition by ion implantation
Lehrstuhl
Universität
Erlangen-Nürnberg
45
Diffusion
 Diffusion Furnaces
Vertical furnace
Lehrstuhl
Universität
Erlangen-Nürnberg
46
Diffusion
 Diffusion Laws after Fick

J  D  grad C
C
 div ( D  grad C )
t
– Diffusions coefficient D
 E 
Di  D0 exp   a 
 kT 
Lehrstuhl
Universität
Erlangen-Nürnberg
47
Diffusion
 Diffusion: Masking with SiO2
– Oxidizing diffusion
Discontinuity of doping concentration
at the interface due to segregation
(chemical potential is continuous)
– Segregation coefficient m
m
C(x)
Si
SiO 2
x=0
x
C1 (0, t )
C2 (0, t )
– Conservation of masses at the interface
D2
C
C2
dx
 D1 1  (m  b )C2 (0, t ) 0
x
x
dt
b: Ratio Si/SiO2
Lehrstuhl
Universität
Erlangen-Nürnberg
48
Silicon Technology











Introduction
Cleanroom
Cleaning
Oxidation
Layer Deposition
Lithography
Etching
Diffusion
Ion Implantation
Lehrstuhl
Universität
Erlangen-Nürnberg
49
Ion Implantation
 Ion implantation is the standard technique for doping in device
manufacturing
 Principle:
–
–
–
–
–
–
ions are generated by impact ionization in a ion source,
are extracted,
are separated by mass in a magnet,
are accelerated,
are deflected electrically or magnetically, and
are implanted into the sample
 Stopping mechanisms:
– Electronic stopping Se
(inelastic)
– Nuclear stopping Sn
(elastic)
Lehrstuhl
Universität
Erlangen-Nürnberg
50
Ion Implantation
 Implantation Equipment
Ion source
Lehrstuhl
Target chamber
Schematic overview
Universität
Erlangen-Nürnberg
51
Ion Implantation
 Implantation Profiles
– Ideal case: Gaussian profile
C( x ) 
 x  R p 2 

exp 
2

2R p 
2 R p

N
• Ion dose N
• Projected range Rp
• Vertical straggle ΔRp
 Annealing
– Damage is caused by nuclear
stopping (displacement of lattice
atoms),
– Thermal treatment at 800-1050°C
anneals damage
Lehrstuhl
Universität
Erlangen-Nürnberg
52
Silicon Technology











Introduction
Cleanroom
Cleaning
Oxidation
Layer Deposition
Lithography
Etching
Diffusion
Ion Implantation
Lehrstuhl
Universität
Erlangen-Nürnberg
53
Wafer manufacturing
Packaging
Wafer test
Contacting external connectors
Dicing
Chip bonding
Final test
Lehrstuhl
Universität
Erlangen-Nürnberg
54
 Separation of Chips by Dicing (Friction sawing)
–
–
–
–
Wafer is laminated and clamped to a frame for dicing
Lamination is just scored while dicing
Water cooling while dicing
Saw blade
• Steel disc with diamond grains (3-7 µm)
• Cutting width: 30-100 µm
saw blade
• Rotation: 15,000-40,000 rpm
coolant
supply
wafer
lamination
dicing table
Lehrstuhl
Universität
Erlangen-Nürnberg
55
 Mounting (gluing) Tested Chips onto Lead Frames
Lehrstuhl
Universität
Erlangen-Nürnberg
56
 Electrical Contact between Chips and Connector Pins
– Ball-Point Bonding:
SEM picture of a Ball-Point Bond connection
Lehrstuhl
Universität
Erlangen-Nürnberg
57
7th Indo-German Winter Academy
Lehrstuhl
Universität
Erlangen-Nürnberg
58

Presentation - Lehrstuhl für Elektronische Bauelemente

Transcrição

Documentos relacionados

Appendix A Ofcom Local TV Transmission mode