PDF, 435,5 KB - Mixed Signal Circuit Design (MSC)

Transcrição

Frequency Synthesizer for Multi-Band MultiStandard Base Station Application
Sabbir A. Osmany, J. Christoph Scheytt
IHP
Im Technologiepark 25
15236 Frankfurt (Oder)
Germany
IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany
www.ihp-microelectronics.com
© 2008 - All rights reserved
Outline
Introduction
Synthesizer architecture
Phase noise in PLLs
Design of subcircuits
Measurement results & comparison (VCO)
Conclusions
Introduction
Variety of wireless standards for different application scenarios
Currently system design ( HW/SW) is done separately for every standard

=> Limited hardware reuse
Feasible standards and frequency bands to be served with one hardware
=> MxMobile ( Multi-Standard Mobile Platform)
Need for One Common Synthesizer Module !
Introduction
700
GSM
1000
TDMA
UMTS
FDD
1800
2500
TDMA
TDMA
FDD
3G LTE
WiMAX
3500 MHz
TDD
TDD
TDD
FDD
And furthers Radio
Frequency bands
in future?
Atleast 11 sub bands have to be served
Tuning range
S S B Noise
Step size
Harmonic spurs
Non-harmonic spurs
…
700 MHz … 4 GHz
-120 dBc/Hz @ 2 MHz
5 MHz
< - 20 dBc
<-65 … -90 dB
…
Introduction
SiGe Technology
High-frequency performance: comparable to GaAs, better than CMOS
Low-frequency phase noise: much better than CMOS, better than GaAs
High-frequency phase noise: better than CMOS (@ same technology node),
inferior to GaAs
Cost: cheaper than GaAs, more expensive than CMOS in volume
SiGe BiCMOS Technology
Combines advantages SiGe HBTs with complexity of CMOS
BiCMOS process allows for combining analog and digital functions
(channel selection) on the same chip
SiGe BiCMOS technology perfectly suited
f
R=2..255
f
REF
VCO1
PFD
R
:
CP
PFD
LF
VCO2
20..28 GHz
f
VCO
:2
M=3/4/5/6/8/10/12/16
:M
N=3 … 2048
700..4400 MHz
N:1
8
serial
interface

11
f out
3
5
3
control register
Type –II, Single loop PLL
VCO frequency ~ 20 - 28 GHz (Qind ~ f, Qvar ~ 1/f )
5 bit digital tuning and fine analog tuning
Low PFD/CP, loop filter noise gain
:3
3.33 – 4.67 GHz
2.5 – 3.5 GHz
:5
2 – 2.8 GHz
:3
1.67 – 2.33 GHz
mux
f out
700..4400 MHz
1.25 – 1.75 GHz
:5
1 – 1.4 GHz
:3
833 – 1167 MHz
VCO1
:2
VCO2
:2
:2
:2
:2
625 – 875 MHz
band selection
20..28 GHz
High-frequency VCOs + high-speed dividers
Low-noise wideband solution
Phase Noise in PLLs
noisy phase of crystal reference
(free-running oscillator)
φREF
PFD
charge
pump
VCO with high phase noise
(phase-locked to reference)
LPF
VCO
φout
_ N

Reference noise = > Low-pass filtered and amplified by N
VCO noise => High-pass filtered
Charge pump noise => Low-pass filtered
Loop filter noise => Band-pass filtered
Phase Noise in PLLs
Reference noise dominantes
Charge pump dominantes
VCO dominantes
PLL phase noise spectrum and
its components
Phase noise for different charge
pump currents
Higher charge pump current reduces in-band phase noise,
2
(charge pump noise PSD ~I CP , transfer function ~ 1 I CP )
Higher current increases phase noise at very large offset
Design of subcircuit (VCO)
Analog
tuning
20..24 GHz
VCO1
Vbb
Vout
Output buffer in
common emitter
configuration
VCO2
24..28 GHz
MIM capacitors
4
1
Digital
tuning
sw1
inv
1 bit core selection, 4 bit digital tuning
sw2
inv
Differential, Colpitts type oscillator
sw3
inv
Usually for digital tuning, MOS switch
is used to ON/OFF mim capacitor
degrade phase noise
sw4
inv
Vctrl
Our approach
use varactor in digital manner
Design of subcircuit (VCO)
Inductor
Varactor
symmetry line
signal
D=160µ
W=20µ
Vctrl
charge extraction (p+)
Gate (Poly-Si, n+)
n+
n-well
Silicon-substrate (p-type)
Fifth Al metal layer (thickness 3 µm)
Simulated Q ~ 20
Accumulation mode varactors
Cmax / Cmin of varactor: ~ 3
Measured quality factor ~ 14
Measurement results (VCO)
S_00000
Tuning curve
S_00001
S_00010
S_00011
29
S_00100
S_00101
28
S_00110
S_00111
S_01000
27
S_01001
S_01010
S_01011
26
S_01100
Freq [GHz]
S_01101
S_01110
25
S_01111
S_10000
24
S_10001
S_10010
S_10011
23
S_10100
S_10101
VCO spectrum
S_10110
22
S_10111
S_11000
S_11001
21
Measured tuning range:
20.4 - 23.8GHz, 25.1 – 28.5GHz
VCC =5V, Ic= 4.5mA
S_11010
S_11011
20
S_11100
0
0.5
1
1.5
2
2.5
3
Vctrl [V]
3.5
S_11101
S_11110
S 11111
VCO tuning curve
-112 dBc/Hz @ 1 MHz
Phase Noise [dBc/Hz]
Measurement results & comparison (VCO)
5
-90
6 dB / octave
-95
1
-100
2
4
3
-105
This work
-110
-100
-10
Frequency [GHz]
Phase noise at 23 GHz operation frequency
Measured phase noise at 1 MHz offset
Measured phase noise is at least 4 dB lower than all previously
published Si-based integrated synthesizers above 12 GHz
Design of subcircuit (Programmable divider)
Program counter
fout
fin
: R / R+1
P
S
Swallow counter
Commonly used programmable divider architecture
Divider value N = P*R+S
Not truely moduler
Design of subcircuit (Programmable divider)
Div value 2n to 2n+1-1
Div value 2n‘min to 2n+1-1
11 bit, div value: 3 to 2048
input frequency 10 GHz
(simulation with parasitic extraction)
1 „A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-m CMOS Technology“, Cicero S.
Vaucher et. al., IEEE Journal of Solid-State Circuits, VOL. 35, NO. 7, JULY 2000
Each CP is based on standard
topology using current mirror
and cascaded current source
down
up
ctrl
ctrl
out
Filter
ctrl
vee
cp_0.5m
vee
down
up
charge pump current
vdd
cp_1m
PFD
out
out
ctrl
Bandwidth and noise can be
optimised by varying the
vdd
down
up
vdd
Current can be controlled
digitally from 250 µA to 3750
µA in steps of 250 µA
cp_2m
vdd
down
up
vee
Four switchable charge pump
currents in parallel
vee
Design of subcircuit (PFD/CP)
cp_0.25m
out
PFD is designed using two
resettable D-flip-flops, nor
gate in the feedback path
Layout
Prog. Div
VCO
SPI
Prescaler
PFD/CP
Chip layout
REF
Area: 4 x 1.4 mm2
High aspect ratio reduces substrate noise coupling significantly
by distance
Vertical guard band between VCO and digital part
Conclusions
Synthesizer architecture for multi-band multi-standard base
station application
32 band VCO measurement results
Using varactor in digital manner helps to achieve better
phase noise
Multi-Modulus divider architecture
Presently complete synthesizer is in the fabrication process
References
1
M. Tiebout, et al., “A Fully Integrated 13GHz DS Fractional-N PLL in 0.13 µm CMOS,” in
IEEE Int. Solid-state Circuits Conf. (ISSCC) Dig. Tech. Papers, vol. 47, 2004, pp. 386-387
2
H. Hashemi, et al., “A 24-GHz SiGe Phased-Array Receiver-LO Phase-Shifting Approach,”
IEEE Tran. Micro. Theory Tech., vol. 53, pp. 614-626, Feb. 2005
3
O. Mazouffre, et al., “A 23-24 GHz Low Power Frequency Synthesizer in 0.25 µm SiGe,” in
Proc. of the 13th European Gallium Arsenide and other Compound Semiconductors Application
Symposium, Paris, France, Oct. 2005, pp. 533-536
4
F. Herzel, S. Glisic, and W. Winkler, “Integrated frequency Synthesizer in SiGe BiCMOS
Technology for 60 and 24 GHz Wireless Applications,” Electronics letters, vol. 43, pp. 154-156,
Feb. 2007.
5
W. Winkler, et al. “A Fully Integrated BiCMOS PLL for 60GHz Wireless Applications,” in IEEE Int.
Solid-state Circuits Conf. (ISSCC) Dig. Tech. Papers, vol. 48, 2005, pp. 406-407
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