Hardware Modelling Coding Styles - Institute of Computer Engineering

Hardware Modelling:
Hardware Description An Overview
Martin Delvai
Content of this course
¾ Hardware Specification
¾ Functional specification
¾ High level requirements document
¾ Detailed design description
¾ Realisation
¾ Hardware description
¾ Hardware implementation
¾ Verification
¾ Review
¾ Formal verification
¾ Functional verification
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Hardware Modelling - Folie 2
Hardware Description: Outline
„
Design entry
„
Level of abstraction
„
Schematic entry vs text-based entry
One possible method to describe hardware
„
VHDL
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„
History
„
Motivation
„
Range of application
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Y-Diagram (1)
Behavior of
the chip
Components inside
the chip
Geometry of
the chip
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Y-Diagram (2)
System Level
Behavior
system
specification
CPU,memory
¾ B: Functionality and constraints
¾ S: Partitioning into subsystems/processes
¾ G: (Motherboard-) Layout
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Structure
chips/board
Geometry
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Y-Diagram (3)
Algoritmic Level
Behavior
processor cores,
bus systems
algorithms
¾ B: Operations and caclulations
ICs/bocks
¾ S: Scheduling and allocation
¾ G: Chip-Layout
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Geometry
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Structure
Y-Diagram (4)
Behavior
Register Transfer Level
ALU, Reg, MUX
register transfer
macrocells
¾ B: Finite State Machines
¾ S: Data and control paths
¾ G: Refined chip layout
Geometry
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Structure
Y-Diagram (5)
Behavior
Structure
Logic Level
boolean equations
and, or, flipflop
standard-cells
¾ B: Boolean functions
¾ S: Netlist
¾ G: Position of standard cells
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Geometry
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Y-Diagram (6)
Behavior
Structure
Circuit Level
Differential equations
Transistors
Mask
¾ B: Differential Equations
¾ S: Transistor network
Geometry
¾ G: ASIC Mask
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Y-Diagram (7)
Behavior
Structure
Chip
• The three views describes
the same system/chip
• The same system/chip can
be defined on all levels of
abstraction
⇒ Level of detail, information content
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Geometry
Y-Table
Behavior
Algorithmic
Level
Logic Level
Circuit Level
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while input
Read „Schilling“
Calulate Euro
Display „Euro“
if A=`1` then
B:= B+1
else
B:= B
end if
D = NOT E
Speicher
I
dU
dI
d2I
=R
+
+ L 2
C
dt
dt
dt
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IO
IN
Control
Speicher
µP
16
8
RAM
IO-Ctrl
B
Translator
OUT
Register
&
>1
A
PS/2
µP
RS232
Interface
PS/2
Interface
IO-Ctrl
A
L
U
R
E
G
Counter
E
C = (D OR B) AND A
CPU
C
RS232
Counter
Register Transfer
Level (RTL)
Inputs : Keyboard
Output: Display
Funktion: .....
Geometry
ALU
System Level
Structure
INV
AND
OR
Hardware Description Languages
System_C
UML
UDL/I
Verilog
VHDL
Very High Speed Integrated Circuit HDL
Graphical Tools/Lang.
ABEL
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History of VHDL
VHSIC ... Very High Speed IC
VHDL ... VHSIC HDL
IEEE ... Institute of Electrical and
Electronics Engineers
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Motivation: Documentation
Documentation for :
• Complex systems
• Maintenance
• Reusability
• Different levels of abstraction
• Readable man-machine interface
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Motivation: Data exchange
Data exchange between:
• Orderer and contractor
• Developers
• Tools
• Computing systems
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Motivation: Complexity (1)
Design Productivity Gap
21%/Yr.
Productivity growth rate
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vs.
58%/Yr.
Complexity growth rate
Motivation: Complexity (2)
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Intel 4004 (1971)
Intel P4 (2001)
• 2300 Transistors
• 12 mm2 / 10µm
• 108 kHz
• 42 Millionen Transistors
• 217 mm2 / 0,18µm
• 2 Ghz
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Motivation: Complexity (3)
Trans. count ratio:
1: 18261
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Range application of VHDL
Behavior
Algorithmic
Level
while input
Testbench
Read „Schilling“
Calulate Euro
Display „Euro“
(VHDL)
if A=`1` then
B:= B+1
else
B:= B
end if
D = NOT E
Speicher
µP
16
Circuit Level
I
dU
dI
d2I
=R
+
+ L 2
C
dt
dt
dt
8
RAM
IO
IN
IO-Ctrl
B
Register
&
>1
A
PS/2
µP
RS232
Interface
PS/2
Interface
IO-Ctrl
R
E
G
C
RS232
Generated
by Tools
(Synplify,
INV
AND
Synopsys)
OR
Generated by tools (Quartus, e.g.)
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Translator
OUT
Counter
E
C = (D OR B) AND A
CPU
Control
VHDL
Logic Level
ECS Group
Speicher
A
L
U
Counter
Register Transfer
Level (RTL)
Inputs : Keyboard
Output: Display
Funktion: .....
Geometry
ALU
System Level
Structure
Summary
• Hardware can be described from different
views: Behavioral, Structural and
Geometrical
• Hardware can be described on different
Levels of Abstraction
• VHDL is one approach to describe
hardware on RTL and Boolean Level
ECS Group
Delvai